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wdenk327f7a02001-11-28 17:49:55 +00001/*
2 * (C) Copyright 2001
3 * Thomas Koeller, tkoeller@gmx.net
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk327f7a02001-11-28 17:49:55 +00006 */
7
8#ifndef __ASSEMBLY__
9#define __ASSEMBLY__ 1
10#endif
11
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020012#include <asm-offsets.h>
wdenk327f7a02001-11-28 17:49:55 +000013#include <config.h>
14#include <asm/processor.h>
15#include <mpc824x.h>
16#include <ppc_asm.tmpl>
17
18#if defined(USE_DINK32)
19 /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020 #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
wdenk327f7a02001-11-28 17:49:55 +000021#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022 #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
wdenk327f7a02001-11-28 17:49:55 +000023#endif
24
25 .text
26
27 /* Values to program into memory controller registers */
28tbl: .long MCCR1, MCCR1VAL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
wdenk327f7a02001-11-28 17:49:55 +000030 .long MCCR3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031 .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
32 (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
33 (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)
wdenk327f7a02001-11-28 17:49:55 +000034 .long MCCR4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035 .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
36 (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
37 (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
38 ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
39 (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
40 (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
41 ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
wdenk327f7a02001-11-28 17:49:55 +000042 .long MSAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
44 (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
45 (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
46 (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000047 .long EMSAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
49 (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
50 (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
51 (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000052 .long MSAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
54 (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
55 (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
56 (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000057 .long EMSAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058 .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
59 (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
60 (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
61 (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000062 .long MEAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
64 (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
65 (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
66 (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000067 .long EMEAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
69 (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
70 (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
71 (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000072 .long MEAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
74 (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
75 (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
76 (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000077 .long EMEAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
79 (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
80 (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
81 (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000082 .long 0
83
84
wdenk327f7a02001-11-28 17:49:55 +000085 /*
86 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
87 * must be done in assembly, since we have no stack at this point.
88 */
89 .global early_init_f
90early_init_f:
91 mflr r10
92
93 /* basic memory controller configuration */
94 lis r3, CONFIG_ADDR_HIGH
95 lis r4, CONFIG_DATA_HIGH
96 bl lab
97lab: mflr r5
98 lwzu r0, tbl - lab(r5)
99loop: lwz r1, 4(r5)
100 stwbrx r0, 0, r3
101 eieio
102 stwbrx r1, 0, r4
103 eieio
104 lwzu r0, 8(r5)
105 cmpli cr0, 0, r0, 0
106 bne cr0, loop
107
108 /* set bank enable bits */
109 lis r0, MBER@h
110 ori r0, 0, MBER@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 li r1, CONFIG_SYS_BANK_ENABLE
wdenk327f7a02001-11-28 17:49:55 +0000112 stwbrx r0, 0, r3
113 eieio
114 stb r1, 0(r4)
115 eieio
116
117 /* delay loop */
118 lis r0, 0x0003
119 mtctr r0
120delay: bdnz delay
121
122 /* enable memory controller */
123 lis r0, MCCR1@h
124 ori r0, 0, MCCR1@l
125 stwbrx r0, 0, r3
126 eieio
127 lwbrx r0, 0, r4
128 oris r0, 0, MCCR1_MEMGO@h
129 stwbrx r0, 0, r4
130 eieio
131
132 /* set up stack pointer */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 lis r1, CONFIG_SYS_INIT_SP_OFFSET@h
134 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
wdenk327f7a02001-11-28 17:49:55 +0000135
136 mtlr r10
137 blr