blob: e7b3c839492a4c2c506eef6ee5713d4b8753e379 [file] [log] [blame]
Heiko Schocherca43ba12007-01-11 15:44:44 +01001/*------------------------------------------------------------------------------+
2 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +01003 * This souce code has been made available to you by EuroDesign
4 * (www.eurodsn.de). It's based on the original IBM source code, so
5 * this follows:
Heiko Schocherca43ba12007-01-11 15:44:44 +01006 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +01007 * This source code has been made available to you by IBM on an AS-IS
8 * basis. Anyone receiving this source is licensed under IBM
9 * copyrights to use it in any way he or she deems fit, including
10 * copying it, modifying it, compiling it, and redistributing it either
11 * with or without modifications. No license under IBM patents or
12 * patent applications is to be implied by the copyright license.
Heiko Schocherca43ba12007-01-11 15:44:44 +010013 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010014 * Any user of this software should understand that IBM cannot provide
15 * technical support for this software and will not be responsible for
16 * any consequences resulting from the use of this software.
Heiko Schocherca43ba12007-01-11 15:44:44 +010017 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010018 * Any person who transfers this source code or any derivative work
19 * must include the IBM copyright notice, this paragraph, and the
20 * preceding two paragraphs in the transferred software.
Heiko Schocherca43ba12007-01-11 15:44:44 +010021 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010022 * COPYRIGHT I B M CORPORATION 1995
23 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
Heiko Schocherca43ba12007-01-11 15:44:44 +010024 *------------------------------------------------------------------------------- */
25
26#include <config.h>
27#include <ppc4xx.h>
28
29#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/**
38 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
39 *
40 * IMPORTANT: For pass1 this code must run from cache since you can not
41 * reliably change a peripheral banks timing register (pbxap) while running
42 * code from that bank. For ex., since we are running from ROM on bank 0, we
43 * can NOT execute the code that modifies bank 0 timings from ROM, so
44 * we run it from cache.
45 *
46 * Bank 0 - Boot-Flash
47 * Bank 1 - NAND-Flash
48 * Bank 2 - ISA bus
49 * Bank 3 - Second Flash
50 * Bank 4 - USB controller
51 */
52 .globl ext_bus_cntlr_init
53ext_bus_cntlr_init:
54/*
55 * We need the current boot up configuration to set correct
56 * timings into internal flash and external flash
57 */
58 mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
Wolfgang Denkf11033e2007-01-15 13:41:04 +010059 0 0 -> 8 bit external ROM
60 0 1 -> 16 bit internal ROM */
Heiko Schocherca43ba12007-01-11 15:44:44 +010061 addi r4,0,2
62 srw r24,r24,r4 /* shift right r24 two positions */
63 andi. r24,r24,0x06000
Wolfgang Denkf11033e2007-01-15 13:41:04 +010064/*
Heiko Schocherca43ba12007-01-11 15:44:44 +010065 * All calculations are based on 33MHz EBC clock.
66 *
67 * First, create a "very slow" timing (~250ns) with burst mode enabled
68 * This is need for the external flash access
69 */
70 lis r25,0x0800
71 ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
72/*
73 * Second, create a fast timing:
74 * 90ns first cycle - 3 clock access
75 * and 90ns burst cycle, plus 1 clock after the last access
76 * This is used for the internal access
77 */
78 lis r26,0x8900
79 ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
80/*
81 * We can't change settings on CS# if we currently use them.
82 * -> load a few instructions into cache and run this code from cache
83 */
84 mflr r4 /* save link register */
85 bl ..getAddr
86..getAddr:
87 mflr r3 /* get address of ..getAddr */
88 mtlr r4 /* restore link register */
89 addi r4,0,14 /* set ctr to 10; used to prefetch */
90 mtctr r4 /* 10 cache lines to fit this function
91 in cache (gives us 8x10=80 instructions) */
92..ebcloop:
93 icbt r0,r3 /* prefetch cache line for addr in r3 */
94 addi r3,r3,32 /* move to next cache line */
95 bdnz ..ebcloop /* continue for 10 cache lines */
96/*
97 * Delay to ensure all accesses to ROM are complete before changing
98 * bank 0 timings. 200usec should be enough.
99 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
100 */
101 lis r3,0x0
102 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
103 mtctr r3
104..spinlp:
105 bdnz ..spinlp /* spin loop */
106
107/*-----------------------------------------------------------------------
108 * Memory Bank 0 (BOOT-ROM) initialization
109 * 0xFFEF00000....0xFFFFFFF
110 * We only have to change the timing. Mapping is ok by boot-strapping
111 *----------------------------------------------------------------------- */
112
113 li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */
114 mtdcr ebccfga,r4
115
116 mr r4,r26 /* assume internal fast flash is boot flash */
117 cmpwi r24,0x2000 /* assumption true? ... */
118 beq 1f /* ...yes! */
119 mr r4,r25 /* ...no, use the slow variant */
120 mr r25,r26 /* use this for the other flash */
1211:
122 mtdcr ebccfgd,r4 /* change timing now */
123
124 li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */
125 mtdcr ebccfga,r4
126 mfdcr r4,ebccfgd
127 lis r3,0x0001
128 ori r3,r3,0x8000 /* allow reads and writes */
129 or r4,r4,r3
130 mtdcr ebccfgd,r4
131
132/*-----------------------------------------------------------------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100133 * Memory Bank 3 (Second-Flash) initialization
Heiko Schocherca43ba12007-01-11 15:44:44 +0100134 * 0xF0000000...0xF01FFFFF -> 2MB
135 *----------------------------------------------------------------------- */
136
137 li r4,pb3ap /* Peripheral Bank 1 Access Parameter */
138 mtdcr ebccfga,r4
139 mtdcr ebccfgd,r2 /* change timing */
140
141 li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */
142 mtdcr ebccfga,r4
143
144 lis r4,0xF003
145 ori r4,r4,0x8000
146/*
147 * Consider boot configuration
148 */
149 xori r24,r24,0x2000 /* invert current bus width */
150 or r4,r4,r24
151 mtdcr ebccfgd,r4
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100152
Heiko Schocherca43ba12007-01-11 15:44:44 +0100153/*-----------------------------------------------------------------------
154 * Memory Bank 1 (NAND-Flash) initialization
155 * 0x77D00000...0x77DFFFFF -> 1MB
156 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
157 * - the setup time is 0ns
158 * - the hold time is 15ns
159 * ->
160 * - TWT = 0
161 * - CSN = 0
162 * - OEN = 0
163 * - WBN = 0
164 * - WBF = 0
165 * - TH = 1
166 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
167 *----------------------------------------------------------------------- */
168
169 li r4,pb1ap /* Peripheral Bank 1 Access Parameter */
170 mtdcr ebccfga,r4
171
172 lis r4,0x0000
173 ori r4,r4,0x0200
174 mtdcr ebccfgd,r4
175
176 li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */
177 mtdcr ebccfga,r4
178
179 lis r4,0x77D1
180 ori r4,r4,0x8000
181 mtdcr ebccfgd,r4
182
183
184/* USB init (without acceleration) */
185#ifndef CONFIG_ISP1161_PRESENT
186 li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
187 mtdcr ebccfga,r4
188 lis r4,0x0180
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100189 ori r4,r4,0x5940
Heiko Schocherca43ba12007-01-11 15:44:44 +0100190 mtdcr ebccfgd,r4
191#endif
192
193/*-----------------------------------------------------------------------
194 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
195 * 0x78000000...0x7BFFFFFF -> 64 MB
196 * Wir arbeiten bei 33 MHz -> 30ns
197 *-----------------------------------------------------------------------
198
199 A7 (ppc notation) or A24 (standard notation) decides about
200 the type of access:
201 A7/A24=0 -> memory cycle
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100202 A7/ /A24=1 -> I/O cycle
Heiko Schocherca43ba12007-01-11 15:44:44 +0100203*/
204 li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */
205 mtdcr ebccfga,r4
206/*
207 We emulate an ISA access
208
209 1. Address active
210 2. wait 0 EBC clocks -> CSN=0
211 3. set CS#
212 4. wait 0 EBC clock -> OEN/WBN=0
213 5. set OE#/WE#
214 6. wait 4 clocks (ca. 90ns) and for Ready signal
215 7. hold for 4 clocks -> TH=4
216*/
217
218#if 1
219/* faster access to isa-bus */
220 lis r4,0x0180
221 ori r4,r4,0x5940
222#else
223 lis r4,0x0100
224 ori r4,r4,0x0340
225#endif
226 mtdcr ebccfgd,r4
227
228#ifdef IDE_USES_ISA_EMULATION
229 li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */
230 mtdcr ebccfga,r25
231 mtdcr ebccfgd,r4
232#endif
233
234 li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */
235 mtdcr ebccfga,r25
236 mtdcr ebccfgd,r4
237 li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */
238 mtdcr ebccfga,r25
239 mtdcr ebccfgd,r4
240
241 li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */
242 mtdcr ebccfga,r25
243
244 lis r4,0x780B
245 ori r4,r4,0xA000
246 mtdcr ebccfgd,r4
247/*
248 * the other areas are only 1MiB in size
249 */
250 lis r4,0x7401
251 ori r4,r4,0xA000
252
253 li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */
254 mtdcr ebccfga,r25
255 lis r4,0x7401
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100256 ori r4,r4,0xA000
Heiko Schocherca43ba12007-01-11 15:44:44 +0100257 mtdcr ebccfgd,r4
258
259 li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */
260 mtdcr ebccfga,r25
261 lis r4,0x7411
262 ori r4,r4,0xA000
263 mtdcr ebccfgd,r4
264
265#ifndef CONFIG_ISP1161_PRESENT
266 li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */
267 mtdcr ebccfga,r25
268 lis r4,0x7421
269 ori r4,r4,0xA000
270 mtdcr ebccfgd,r4
271#endif
272#ifdef IDE_USES_ISA_EMULATION
273 li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */
274 mtdcr ebccfga,r25
275 lis r4,0x0000
276 ori r4,r4,0x0000
277 mtdcr ebccfgd,r4
278#endif
279
280/*-----------------------------------------------------------------------
281 * Memory bank 4: USB controller Philips ISP6111
282 * 0x77C00000 ... 0x77CFFFFF
283 *
284 * The chip is connected to:
285 * - CPU CS#4
286 * - CPU IRQ#2
287 * - CPU DMA 3
288 *
289 * Timing:
290 * - command to first data: 300ns. Software must ensure this timing!
291 * - Write pulse: 26ns
292 * - Read pulse: 33ns
293 * - read cycle time: 150ns
294 * - write cycle time: 140ns
295 *
296 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
297 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100298 * |- 300ns --|
299 * |---- 420ns ---|---- 420ns ---| cycle
Heiko Schocherca43ba12007-01-11 15:44:44 +0100300 * CS ############:###____#######:###____#######
301 * OE ############:####___#######:####___#######
302 * WE ############:####__########:####__########
303 *
304 * ----> 2 clocks RD/WR pulses: 60ns
305 * ----> CSN: 3 clock, 90ns
306 * ----> OEN: 1 clocks (read cycle)
307 * ----> WBN: 1 clocks (write cycle)
308 * ----> WBE: 2 clocks
309 * ----> TH: 7 clock, 210ns
310 * ----> TWT: 7 clocks
311 *----------------------------------------------------------------------- */
312
313#ifdef CONFIG_ISP1161_PRESENT
314
315 li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
316 mtdcr ebccfga,r4
317
318 lis r4,0x030D
319 ori r4,r4,0x5E80
320 mtdcr ebccfgd,r4
321
322 li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */
323 mtdcr ebccfga,r4
324
325 lis r4,0x77C1
326 ori r4,r4,0xA000
327 mtdcr ebccfgd,r4
328
329#endif
330
331#ifndef IDE_USES_ISA_EMULATION
332
333/*-----------------------------------------------------------------------
334 * Memory Bank 5 used for IDE access
335 *
336 * Timings for IDE Interface
337 *
338 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
339 * 70 165 30 PIO-Mode 0, [ns]
340 * 3 6 1 [Cycles] ----> AP=0x040C0200
341 * 50 125 20 PIO-Mode 1, [ns]
342 * 2 5 1 [Cycles] ----> AP=0x03080200
343 * 30 100 15 PIO-Mode 2, [ns]
344 * 1 4 1 [Cycles] ----> AP=0x02040200
345 * 30 80 10 PIO-Mode 3, [ns]
346 * 1 3 1 [Cycles] ----> AP=0x01840200
347 * 25 70 10 PIO-Mode 4, [ns]
348 * 1 3 1 [Cycles] ----> AP=0x01840200
349 *
350 *----------------------------------------------------------------------- */
351
352 li r4,pb5ap
353 mtdcr ebccfga,r4
354 lis r4,0x040C
355 ori r4,r4,0x0200
356 mtdcr ebccfgd,r4
357
358 li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */
359 mtdcr ebccfga,r4
360
361 lis r4,0x7A01
362 ori r4,r4,0xA000
363 mtdcr ebccfgd,r4
364#endif
365/*
366 * External Peripheral Control Register
367 */
368 li r4,epcr
369 mtdcr ebccfga,r4
370
371 lis r4,0xB84E
372 ori r4,r4,0xF000
373 mtdcr ebccfgd,r4
374/*
375 * drive POST code
376 */
377 lis r4,0x7900
378 ori r4,r4,0x0080
379 li r3,0x0001
380 stb r3,0(r4) /* 01 -> external bus controller is initialized */
381 nop /* pass2 DCR errata #8 */
382 blr