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Ramneek Mehreshba92ee02015-05-29 14:47:19 +05301/*
Rajesh Bhagat707c8662016-07-01 18:51:47 +05302 * Copyright 2015,2016 Freescale Semiconductor, Inc.
Ramneek Mehreshba92ee02015-05-29 14:47:19 +05303 *
4 * FSL USB HOST xHCI Controller
5 *
6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <usb.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090013#include <linux/errno.h>
Ramneek Mehreshba92ee02015-05-29 14:47:19 +053014#include <linux/compat.h>
15#include <linux/usb/xhci-fsl.h>
16#include <linux/usb/dwc3.h>
17#include "xhci.h"
Sriram Dashef53b8c2016-06-13 09:58:36 +053018#include <fsl_errata.h>
19#include <fsl_usb.h>
Rajesh Bhagat707c8662016-07-01 18:51:47 +053020#include <dm.h>
Ramneek Mehreshba92ee02015-05-29 14:47:19 +053021
22/* Declare global data pointer */
23DECLARE_GLOBAL_DATA_PTR;
24
Rajesh Bhagat707c8662016-07-01 18:51:47 +053025#ifndef CONFIG_DM_USB
Ramneek Mehreshba92ee02015-05-29 14:47:19 +053026static struct fsl_xhci fsl_xhci;
27unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
Rajesh Bhagat707c8662016-07-01 18:51:47 +053028#else
29struct xhci_fsl_priv {
30 struct xhci_ctrl xhci;
31 fdt_addr_t hcd_base;
32 struct fsl_xhci ctx;
33};
34#endif
Ramneek Mehreshba92ee02015-05-29 14:47:19 +053035
36__weak int __board_usb_init(int index, enum usb_init_type init)
37{
38 return 0;
39}
40
Sriram Dashef53b8c2016-06-13 09:58:36 +053041static int erratum_a008751(void)
42{
Priyanka Jain3049a582017-04-27 15:08:07 +053043#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
44 defined(CONFIG_TARGET_LS2080AQDS)
Sriram Dashef53b8c2016-06-13 09:58:36 +053045 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
46 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
47 return 0;
48#endif
49 return 1;
50}
51
52static void fsl_apply_xhci_errata(void)
53{
54 int ret;
55 if (has_erratum_a008751()) {
56 ret = erratum_a008751();
57 if (ret != 0)
58 puts("Failed to apply erratum a008751\n");
59 }
60}
61
Sriram Dashe9157162016-08-22 17:55:15 +053062static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
63{
64 clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
65 USB3_ENABLE_BEAT_BURST);
66 setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
67}
68
Ramneek Mehreshba92ee02015-05-29 14:47:19 +053069static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
70{
71 int ret = 0;
72
73 ret = dwc3_core_init(fsl_xhci->dwc3_reg);
74 if (ret) {
75 debug("%s:failed to initialize core\n", __func__);
76 return ret;
77 }
78
79 /* We are hard-coding DWC3 core to Host Mode */
80 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
81
Nikhil Badola667f4dd2015-06-23 09:17:49 +053082 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
83 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
84
Sriram Dashe9157162016-08-22 17:55:15 +053085 /* Change beat burst and outstanding pipelined transfers requests */
86 fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
87
Sriram Dash4c043712016-09-23 12:57:52 +053088 /*
89 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
90 * reliably support Rx Detect in P3 mode(P3 is the default
91 * setting). Therefore, some USB3.0 devices may not be detected
92 * reliably in Super Speed mode. So, USB controller to configure
93 * USB in P2 mode whenever the Receive Detect feature is required.
94 * whenever the Receive Detect feature is required.
95 */
96 if (has_erratum_a010151())
97 clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
98 DWC3_GUSB3PIPECTL_DISRXDETP3,
99 DWC3_GUSB3PIPECTL_DISRXDETP3);
100
Ramneek Mehreshba92ee02015-05-29 14:47:19 +0530101 return ret;
102}
103
104static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
105{
106 /*
107 * Currently fsl socs do not support PHY shutdown from
108 * sw. But this support may be added in future socs.
109 */
110 return 0;
111}
112
Rajesh Bhagat707c8662016-07-01 18:51:47 +0530113#ifdef CONFIG_DM_USB
114static int xhci_fsl_probe(struct udevice *dev)
115{
116 struct xhci_fsl_priv *priv = dev_get_priv(dev);
117 struct xhci_hccr *hccr;
118 struct xhci_hcor *hcor;
119
120 int ret = 0;
121
122 /*
123 * Get the base address for XHCI controller from the device node
124 */
Simon Glassa821c4a2017-05-17 17:18:05 -0600125 priv->hcd_base = devfdt_get_addr(dev);
Rajesh Bhagat707c8662016-07-01 18:51:47 +0530126 if (priv->hcd_base == FDT_ADDR_T_NONE) {
127 debug("Can't get the XHCI register base address\n");
128 return -ENXIO;
129 }
130 priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
131 priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
132 DWC3_REG_OFFSET);
133
134 fsl_apply_xhci_errata();
135
136 ret = fsl_xhci_core_init(&priv->ctx);
137 if (ret < 0) {
138 puts("Failed to initialize xhci\n");
139 return ret;
140 }
141
142 hccr = (struct xhci_hccr *)(priv->ctx.hcd);
143 hcor = (struct xhci_hcor *)((uintptr_t) hccr
144 + HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
145
146 debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
147 (uintptr_t)hccr, (uintptr_t)hcor,
148 (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
149
150 return xhci_register(dev, hccr, hcor);
151}
152
153static int xhci_fsl_remove(struct udevice *dev)
154{
155 struct xhci_fsl_priv *priv = dev_get_priv(dev);
Rajesh Bhagat707c8662016-07-01 18:51:47 +0530156
157 fsl_xhci_core_exit(&priv->ctx);
158
Masahiro Yamada8319aeb2016-09-06 22:17:35 +0900159 return xhci_deregister(dev);
Rajesh Bhagat707c8662016-07-01 18:51:47 +0530160}
161
162static const struct udevice_id xhci_usb_ids[] = {
163 { .compatible = "fsl,layerscape-dwc3", },
164 { }
165};
166
167U_BOOT_DRIVER(xhci_fsl) = {
168 .name = "xhci_fsl",
169 .id = UCLASS_USB,
170 .of_match = xhci_usb_ids,
171 .probe = xhci_fsl_probe,
172 .remove = xhci_fsl_remove,
173 .ops = &xhci_usb_ops,
174 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
175 .priv_auto_alloc_size = sizeof(struct xhci_fsl_priv),
176 .flags = DM_FLAG_ALLOC_PRIV_DMA,
177};
178#else
Ramneek Mehreshba92ee02015-05-29 14:47:19 +0530179int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
180{
181 struct fsl_xhci *ctx = &fsl_xhci;
182 int ret = 0;
183
184 ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
185 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
186
187 ret = board_usb_init(index, USB_INIT_HOST);
188 if (ret != 0) {
189 puts("Failed to initialize board for USB\n");
190 return ret;
191 }
192
Sriram Dashef53b8c2016-06-13 09:58:36 +0530193 fsl_apply_xhci_errata();
194
Ramneek Mehreshba92ee02015-05-29 14:47:19 +0530195 ret = fsl_xhci_core_init(ctx);
196 if (ret < 0) {
197 puts("Failed to initialize xhci\n");
198 return ret;
199 }
200
201 *hccr = (struct xhci_hccr *)ctx->hcd;
Nikhil Badola7e5a32f2015-06-23 09:17:32 +0530202 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr
Ramneek Mehreshba92ee02015-05-29 14:47:19 +0530203 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
204
Nikhil Badola7e5a32f2015-06-23 09:17:32 +0530205 debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
206 (uintptr_t)*hccr, (uintptr_t)*hcor,
207 (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
Ramneek Mehreshba92ee02015-05-29 14:47:19 +0530208
209 return ret;
210}
211
212void xhci_hcd_stop(int index)
213{
214 struct fsl_xhci *ctx = &fsl_xhci;
215
216 fsl_xhci_core_exit(ctx);
217}
Rajesh Bhagat707c8662016-07-01 18:51:47 +0530218#endif