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wdenk7a8e9bed2003-05-31 18:35:21 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_X86 1 /* This is a X86 CPU */
37#define CONFIG_SC520 1 /* Include support for AMD SC520 */
38
39#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
40#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
41#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */
42
43/* define at most one of these */
44#undef CFG_SDRAM_CAS_LATENCY_2T
45#define CFG_SDRAM_CAS_LATENCY_3T
46
47#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
48#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */
49#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */
50#undef CFG_TIMER_SC520 /* use SC520 swtimers */
51#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */
52#undef CFG_TIMER_TSC /* use the Pentium TSC timers */
53
54#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */
55
56#define CONFIG_SHOW_BOOT_PROGRESS 1
57#define CONFIG_LAST_STAGE_INIT 1
58
59/*
60 * Size of malloc() pool
61 */
62#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
63
64
65#define CONFIG_BAUDRATE 9600
66
67#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM)
68
69/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
70#include <cmd_confdefs.h>
71
72#define CONFIG_BOOTDELAY 15
73#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
74#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
75
76#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
77#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
78#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
79#endif
80
81
82/*
83 * Miscellaneous configurable options
84 */
85#define CFG_LONGHELP /* undef to save memory */
86#define CFG_PROMPT "boot > " /* Monitor Command Prompt */
87#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
88#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
89#define CFG_MAXARGS 16 /* max number of command args */
90#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
91
92#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
93#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
94
95#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
96
97#define CFG_LOAD_ADDR 0x100000 /* default load address */
98
99#define CFG_HZ 1024 /* incrementer freq: 1kHz */
100
101 /* valid baudrates */
102#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
103
104
105/*-----------------------------------------------------------------------
106 * Physical Memory Map
107 */
108#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */
109
110/*-----------------------------------------------------------------------
111 * FLASH and environment organization
112 */
113
114
115#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
116#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
117
118/* timeout values are in ticks */
119#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
120#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
121
122
123#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */
124#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */
125#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */
126
127
128/* allow to overwrite serial and ethaddr */
129#define CONFIG_ENV_OVERWRITE
130
131
132#if 0
133/* Environment in flash */
134#define CFG_ENV_IS_IN_FLASH 1
135# define CFG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */
136# define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */
137# define CFG_ENV_OFFSET 0
138
139#else
140/* Environment in EEPROM */
141
142# define CFG_ENV_IS_IN_EEPROM 1
143# define CONFIG_SPI
144# define CONFIG_SPI_X 1
145# define CFG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */
146# define CFG_ENV_OFFSET 0x1c00
147
148#endif
149
150#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
151#define CFG_JFFS2_NUM_BANKS 1 /* */
152
153/*-----------------------------------------------------------------------
154 * Device drivers
155 */
156#define CONFIG_NET_MULTI /* Multi ethernet cards support */
157#define CONFIG_EEPRO100
158
159/************************************************************
160 * IDE/ATA stuff
161 ************************************************************/
162#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
163#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
164#define CFG_ATA_BASE_ADDR 0
165#define CFG_ATA_IDE0_OFFSET 0x01f0 /* ide0 offset */
166#define CFG_ATA_IDE1_OFFSET 0xe000 /* ide1 offset */
167#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
168#define CFG_ATA_REG_OFFSET 0 /* reg offset */
169#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
170
171#define CFG_FISRT_PCMCIA_BUS 1
172
173#undef CONFIG_IDE_LED /* no led for ide supported */
174#undef CONFIG_IDE_RESET /* reset for ide unsupported... */
175#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
176
177#define CONFIG_IDE_TI_CARDBUS
178#define CFG_PCMCIA_CIS_WIN 0x27f00000
179#define CFG_PCMCIA_CIS_WIN_SIZE 0x00100000
180#define CFG_PCMCIA_IO_WIN 0xe000
181#define CFG_PCMCIA_IO_WIN_SIZE 16
182
183/************************************************************
184 * DISK Partition support
185 ************************************************************/
186#define CONFIG_DOS_PARTITION
187#define CONFIG_MAC_PARTITION
188#define CONFIG_ISO_PARTITION /* Experimental */
189
190
191
192
193/************************************************************
194 * RTC
195 ***********************************************************/
196#define CONFIG_RTC_MC146818
197#undef CONFIG_WATCHDOG /* watchdog disabled */
198
199/*
200 * PCI stuff
201 */
202#define CONFIG_PCI /* include pci support */
203#define CONFIG_PCI_PNP /* pci plug-and-play */
204#define CONFIG_PCI_SCAN_SHOW
205
206#define CFG_FIRST_PCI_IRQ 9
207#define CFG_SECOND_PCI_IRQ 10
208#define CFG_THIRD_PCI_IRQ 11
209#define CFG_FORTH_PCI_IRQ 12
210
211
212#endif /* __CONFIG_H */