blob: e6379a3d0de8c1e10f716ecdee885453603465c5 [file] [log] [blame]
Calvin Johnson7ab16472018-03-08 15:30:30 +05301/*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier:GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <asm/io.h>
11#include <netdev.h>
12#include <fm_eth.h>
13#include <fsl_mdio.h>
14#include <malloc.h>
15#include <asm/types.h>
16#include <fsl_dtsec.h>
17#include <asm/arch/soc.h>
18#include <asm/arch-fsl-layerscape/config.h>
19#include <asm/arch-fsl-layerscape/immap_lsch2.h>
20#include <asm/arch/fsl_serdes.h>
21#include <net/pfe_eth/pfe_eth.h>
22#include <dm/platform_data/pfe_dm_eth.h>
23#include <i2c.h>
24
25#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
26
27static inline void ls1012ardb_reset_phy(void)
28{
29 /* Through reset IO expander reset both RGMII and SGMII PHYs */
30 i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
31 i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
32 mdelay(10);
33 i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
34 mdelay(10);
35 i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
36 mdelay(50);
37}
38
39int pfe_eth_board_init(struct udevice *dev)
40{
41 static int init_done;
42 struct mii_dev *bus;
43 struct pfe_mdio_info mac_mdio_info;
44 struct pfe_eth_dev *priv = dev_get_priv(dev);
45
46 if (!init_done) {
47 ls1012ardb_reset_phy();
48 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
49 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
50
51 bus = pfe_mdio_init(&mac_mdio_info);
52 if (!bus) {
53 printf("Failed to register mdio\n");
54 return -1;
55 }
56 init_done = 1;
57 }
58
59 pfe_set_mdio(priv->gemac_port,
60 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
61
62 if (!priv->gemac_port) {
63 /* MAC1 */
64 pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
65 PHY_INTERFACE_MODE_SGMII);
66 } else {
67 /* MAC2 */
68 pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
69 PHY_INTERFACE_MODE_RGMII_TXID);
70 }
71 return 0;
72}
73
74static struct pfe_eth_pdata pfe_pdata0 = {
75 .pfe_eth_pdata_mac = {
76 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
77 .phy_interface = 0,
78 },
79
80 .pfe_ddr_addr = {
81 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
82 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
83 },
84};
85
86static struct pfe_eth_pdata pfe_pdata1 = {
87 .pfe_eth_pdata_mac = {
88 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
89 .phy_interface = 1,
90 },
91
92 .pfe_ddr_addr = {
93 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
94 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
95 },
96};
97
98U_BOOT_DEVICE(ls1012a_pfe0) = {
99 .name = "pfe_eth",
100 .platdata = &pfe_pdata0,
101};
102
103U_BOOT_DEVICE(ls1012a_pfe1) = {
104 .name = "pfe_eth",
105 .platdata = &pfe_pdata1,
106};