Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 CompuLab, Ltd. |
| 4 | * Author: Igor Grinberg <grinberg@compulab.co.il> |
| 5 | * |
| 6 | * Configuration settings for the CompuLab CM-T3517 board |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H |
| 10 | #define __CONFIG_H |
| 11 | |
| 12 | /* |
| 13 | * High Level Configuration Options |
| 14 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 15 | #define CONFIG_CM_T3517 /* working with CM-T3517 */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 16 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 17 | /* |
| 18 | * This is needed for the DMA stuff. |
| 19 | * Although the default iss 64, we still define it |
| 20 | * to be on the safe side once the default is changed. |
| 21 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 22 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 23 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
Nishanth Menon | 987ec58 | 2015-03-09 17:12:04 -0500 | [diff] [blame] | 24 | #include <asm/arch/omap.h> |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 25 | |
Dmitry Lifshitz | f3b44e8 | 2015-09-09 11:27:17 +0300 | [diff] [blame] | 26 | #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 |
| 27 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 28 | /* Clock Defines */ |
| 29 | #define V_OSCK 26000000 /* Clock output from T2 */ |
| 30 | #define V_SCLK (V_OSCK >> 1) |
| 31 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 32 | /* |
| 33 | * The early kernel mapping on ARM currently only maps from the base of DRAM |
| 34 | * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. |
| 35 | * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, |
| 36 | * so that leaves DRAM base to DRAM base + 0x4000 available. |
| 37 | */ |
| 38 | #define CONFIG_SYS_BOOTMAPSZ 0x4000 |
| 39 | |
| 40 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 41 | #define CONFIG_SETUP_MEMORY_TAGS |
| 42 | #define CONFIG_INITRD_TAG |
| 43 | #define CONFIG_REVISION_TAG |
| 44 | #define CONFIG_SERIAL_TAG |
| 45 | |
| 46 | /* |
| 47 | * Size of malloc() pool |
| 48 | */ |
Dmitry Lifshitz | 2f6e4bf | 2015-09-09 11:25:39 +0300 | [diff] [blame] | 49 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 50 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
| 51 | |
| 52 | /* |
| 53 | * Hardware drivers |
| 54 | */ |
| 55 | |
| 56 | /* |
| 57 | * NS16550 Configuration |
| 58 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_NS16550_SERIAL |
| 60 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 61 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
| 62 | |
| 63 | /* |
| 64 | * select serial console configuration |
| 65 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 67 | |
| 68 | /* allow to overwrite serial and ethaddr */ |
| 69 | #define CONFIG_ENV_OVERWRITE |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 71 | 115200} |
| 72 | |
Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 73 | /* USB */ |
Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 74 | |
| 75 | #ifndef CONFIG_USB_MUSB_AM35X |
Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 76 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 |
| 77 | #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 |
Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 78 | #endif /* CONFIG_USB_MUSB_AM35X */ |
| 79 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 80 | /* commands to include */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 81 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 82 | #define CONFIG_SYS_I2C |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 83 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
| 84 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 85 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 |
| 86 | #define CONFIG_I2C_MULTI_BUS |
| 87 | |
| 88 | /* |
| 89 | * Board NAND Info. |
| 90 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 91 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
| 92 | /* to access nand at */ |
| 93 | /* CS0 */ |
| 94 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
| 95 | /* devices */ |
| 96 | |
| 97 | /* Environment information */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 98 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 99 | "loadaddr=0x82000000\0" \ |
| 100 | "baudrate=115200\0" \ |
| 101 | "console=ttyO2,115200n8\0" \ |
Dmitry Lifshitz | e093d0b | 2015-09-08 09:50:00 +0300 | [diff] [blame] | 102 | "netretry=yes\0" \ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 103 | "mpurate=auto\0" \ |
| 104 | "vram=12M\0" \ |
| 105 | "dvimode=1024x768MR-16@60\0" \ |
| 106 | "defaultdisplay=dvi\0" \ |
| 107 | "mmcdev=0\0" \ |
| 108 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ |
| 109 | "mmcrootfstype=ext4\0" \ |
| 110 | "nandroot=/dev/mtdblock4 rw\0" \ |
| 111 | "nandrootfstype=ubifs\0" \ |
| 112 | "mmcargs=setenv bootargs console=${console} " \ |
| 113 | "mpurate=${mpurate} " \ |
| 114 | "vram=${vram} " \ |
| 115 | "omapfb.mode=dvi:${dvimode} " \ |
| 116 | "omapdss.def_disp=${defaultdisplay} " \ |
| 117 | "root=${mmcroot} " \ |
| 118 | "rootfstype=${mmcrootfstype}\0" \ |
| 119 | "nandargs=setenv bootargs console=${console} " \ |
| 120 | "mpurate=${mpurate} " \ |
| 121 | "vram=${vram} " \ |
| 122 | "omapfb.mode=dvi:${dvimode} " \ |
| 123 | "omapdss.def_disp=${defaultdisplay} " \ |
| 124 | "root=${nandroot} " \ |
| 125 | "rootfstype=${nandrootfstype}\0" \ |
| 126 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
| 127 | "bootscript=echo Running bootscript from mmc ...; " \ |
| 128 | "source ${loadaddr}\0" \ |
| 129 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
| 130 | "mmcboot=echo Booting from mmc ...; " \ |
| 131 | "run mmcargs; " \ |
| 132 | "bootm ${loadaddr}\0" \ |
| 133 | "nandboot=echo Booting from nand ...; " \ |
| 134 | "run nandargs; " \ |
| 135 | "nand read ${loadaddr} 2a0000 400000; " \ |
| 136 | "bootm ${loadaddr}\0" \ |
| 137 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 138 | #define CONFIG_BOOTCOMMAND \ |
| 139 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
| 140 | "if run loadbootscript; then " \ |
| 141 | "run bootscript; " \ |
| 142 | "else " \ |
| 143 | "if run loaduimage; then " \ |
| 144 | "run mmcboot; " \ |
| 145 | "else run nandboot; " \ |
| 146 | "fi; " \ |
| 147 | "fi; " \ |
| 148 | "else run nandboot; fi" |
| 149 | |
| 150 | /* |
| 151 | * Miscellaneous configurable options |
| 152 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 153 | #define CONFIG_TIMESTAMP |
| 154 | #define CONFIG_SYS_AUTOLOAD "no" |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 155 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 157 | |
| 158 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) |
| 159 | |
| 160 | /* |
| 161 | * AM3517 has 12 GP timers, they can be driven by the system clock |
| 162 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
| 163 | * This rate is divided by a local divisor. |
| 164 | */ |
| 165 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
| 166 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
| 167 | #define CONFIG_SYS_HZ 1000 |
| 168 | |
| 169 | /*----------------------------------------------------------------------- |
| 170 | * Physical Memory Map |
| 171 | */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 172 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
| 173 | #define CONFIG_SYS_CS0_SIZE (256 << 20) |
| 174 | |
| 175 | /*----------------------------------------------------------------------- |
| 176 | * FLASH and environment organization |
| 177 | */ |
| 178 | |
| 179 | /* **** PISMO SUPPORT *** */ |
| 180 | /* Monitor at start of flash */ |
| 181 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 182 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
| 183 | |
Adam Ford | 7672d9d | 2017-09-04 21:08:02 -0500 | [diff] [blame] | 184 | #define CONFIG_ENV_OFFSET 0x260000 |
| 185 | #define CONFIG_ENV_ADDR 0x260000 |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 186 | |
Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 187 | #if defined(CONFIG_CMD_NET) |
Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 188 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII |
Dmitry Lifshitz | e093d0b | 2015-09-08 09:50:00 +0300 | [diff] [blame] | 189 | #define CONFIG_ARP_TIMEOUT 200UL |
| 190 | #define CONFIG_NET_RETRY_COUNT 5 |
Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 191 | #endif /* CONFIG_CMD_NET */ |
| 192 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 193 | /* additions for new relocation code, must be added to all boards */ |
| 194 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 195 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
| 196 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
| 197 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 198 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 199 | GENERATED_GBL_DATA_SIZE) |
| 200 | |
| 201 | /* Status LED */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 202 | #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 203 | |
Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 204 | /* Display Configuration */ |
Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 205 | #define LCD_BPP LCD_COLOR16 |
| 206 | |
Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 207 | #define CONFIG_SPLASH_SCREEN |
| 208 | #define CONFIG_SPLASHIMAGE_GUARD |
Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 209 | #define CONFIG_BMP_16BPP |
| 210 | #define CONFIG_SCF0403_LCD |
| 211 | |
Nikita Kiryanov | 19a90ed | 2016-04-16 17:55:08 +0300 | [diff] [blame] | 212 | /* EEPROM */ |
Nikita Kiryanov | 19a90ed | 2016-04-16 17:55:08 +0300 | [diff] [blame] | 213 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
| 214 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 215 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
| 216 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 217 | #define CONFIG_SYS_EEPROM_SIZE 256 |
| 218 | |
Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 219 | #endif /* __CONFIG_H */ |