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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher67fa8c22010-02-22 16:43:02 +05302/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
6 *
7 * (C) Copyright 2009
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
Holger Brunck8170aef2012-07-05 05:37:46 +000010 * (C) Copyright 2011-2012
11 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
12 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
Heiko Schocher67fa8c22010-02-22 16:43:02 +053013 */
14
15/*
16 * for linking errors see
17 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
18 */
19
Holger Brunck83b40c32011-06-16 18:11:15 +053020#ifndef _CONFIG_KM_KIRKWOOD_H
21#define _CONFIG_KM_KIRKWOOD_H
Heiko Schocher67fa8c22010-02-22 16:43:02 +053022
Holger Brunck48ced622012-07-05 05:05:06 +000023/* KM_KIRKWOOD */
Holger Brunck8170aef2012-07-05 05:37:46 +000024#if defined(CONFIG_KM_KIRKWOOD)
Mario Six5bc05432018-03-28 14:38:20 +020025#define CONFIG_HOSTNAME "km_kirkwood"
Holger Brunck48ced622012-07-05 05:05:06 +000026#define CONFIG_KM_DISABLE_PCIE
Heiko Schocherf3e93612012-10-25 11:07:00 +020027#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck48ced622012-07-05 05:05:06 +000028
29/* KM_KIRKWOOD_PCI */
Holger Brunck8170aef2012-07-05 05:37:46 +000030#elif defined(CONFIG_KM_KIRKWOOD_PCI)
Mario Six5bc05432018-03-28 14:38:20 +020031#define CONFIG_HOSTNAME "km_kirkwood_pci"
Heiko Schocherf3e93612012-10-25 11:07:00 +020032#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck48ced622012-07-05 05:05:06 +000033#define CONFIG_KM_FPGA_CONFIG
Holger Brunck58c90c82014-08-15 10:51:48 +020034#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
35#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck48ced622012-07-05 05:05:06 +000036
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020037/* KM_KIRKWOOD_128M16 */
38#elif defined(CONFIG_KM_KIRKWOOD_128M16)
Mario Six5bc05432018-03-28 14:38:20 +020039#define CONFIG_HOSTNAME "km_kirkwood_128m16"
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020040#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090041#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020042#define CONFIG_KM_DISABLE_PCIE
Holger Bruncke28d4a22013-10-07 15:10:03 +020043#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020044
Gerlando Falauto9c134e12014-02-13 16:43:00 +010045/* KM_NUSA / KM_SUGP1 */
46#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
Heiko Schocherf3e93612012-10-25 11:07:00 +020047#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Gerlando Falauto9c134e12014-02-13 16:43:00 +010048
49# if defined(CONFIG_KM_NUSA)
Mario Six5bc05432018-03-28 14:38:20 +020050#define CONFIG_HOSTNAME "kmnusa"
Gerlando Falauto9c134e12014-02-13 16:43:00 +010051# elif defined(CONFIG_KM_SUGP1)
Mario Six5bc05432018-03-28 14:38:20 +020052#define CONFIG_HOSTNAME "kmsugp1"
Gerlando Falauto9c134e12014-02-13 16:43:00 +010053#define KM_PCIE_RESET_MPP7
54#endif
55
Holger Brunck8170aef2012-07-05 05:37:46 +000056#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090057#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Holger Brunck8170aef2012-07-05 05:37:46 +000058#define CONFIG_KM_ENV_IS_IN_SPI_NOR
59#define CONFIG_KM_FPGA_CONFIG
60#define CONFIG_KM_PIGGY4_88E6352
Valentin Longchampbe3e8be2012-08-16 01:25:20 +000061#define CONFIG_MV88E6352_SWITCH
62#define CONFIG_KM_MVEXTSW_ADDR 0x10
Holger Brunck8170aef2012-07-05 05:37:46 +000063
Holger Brunckf9454392012-07-05 05:05:03 +000064/* KM_MGCOGE3UN */
65#elif defined(CONFIG_KM_MGCOGE3UN)
Mario Six5bc05432018-03-28 14:38:20 +020066#define CONFIG_HOSTNAME "mgcoge3un"
Heiko Schocherf3e93612012-10-25 11:07:00 +020067#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckf9454392012-07-05 05:05:03 +000068#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090069#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
Holger Brunckf9454392012-07-05 05:05:03 +000070#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
71#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
72#define CONFIG_KM_DISABLE_PCIE
73#define CONFIG_KM_PIGGY4_88E6061
74
75/* KMCOGE5UN */
Holger Brunckd9354532012-07-05 05:05:02 +000076#elif defined(CONFIG_KM_COGE5UN)
Heiko Schocherf3e93612012-10-25 11:07:00 +020077#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckd9354532012-07-05 05:05:02 +000078#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090079#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
Holger Brunckd9354532012-07-05 05:05:02 +000080#define CONFIG_KM_ENV_IS_IN_SPI_NOR
81#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
Mario Six5bc05432018-03-28 14:38:20 +020082#define CONFIG_HOSTNAME "kmcoge5un"
Holger Brunckd9354532012-07-05 05:05:02 +000083#define CONFIG_KM_DISABLE_PCIE
84#define CONFIG_KM_PIGGY4_88E6352
Holger Brunck6ef64862012-07-05 05:05:04 +000085
86/* KM_PORTL2 */
87#elif defined(CONFIG_KM_PORTL2)
Mario Six5bc05432018-03-28 14:38:20 +020088#define CONFIG_HOSTNAME "portl2"
Heiko Schocherf3e93612012-10-25 11:07:00 +020089#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck6ef64862012-07-05 05:05:04 +000090#define CONFIG_KM_PIGGY4_88E6061
91
Holger Brunck90639fe2013-01-15 22:51:22 +000092/* KM_SUV31 */
93#elif defined(CONFIG_KM_SUV31)
Heiko Schocherea818db2013-01-29 08:53:15 +010094#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Mario Six5bc05432018-03-28 14:38:20 +020095#define CONFIG_HOSTNAME "kmsuv31"
Holger Brunck2a4ebef2014-01-27 16:58:24 +010096#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090097#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Holger Brunck90639fe2013-01-15 22:51:22 +000098#define CONFIG_KM_ENV_IS_IN_SPI_NOR
99#define CONFIG_KM_FPGA_CONFIG
Holger Brunck58c90c82014-08-15 10:51:48 +0200100#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
101#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck8170aef2012-07-05 05:37:46 +0000102#else
103#error ("Board unsupported")
104#endif
105
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530106/* include common defines/options for all arm based Keymile boards */
Valentin Longchamp264eaa02011-05-04 01:47:33 +0000107#include "km/km_arm.h"
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530108
Holger Brunck8170aef2012-07-05 05:37:46 +0000109#if defined(CONFIG_KM_PIGGY4_88E6352)
110/*
111 * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
112 * an Marvell 88E6352 simple switch.
113 * In this case we have to change the default settings for the etherent mac.
114 * There is NO ethernet phy. The ARM and Switch are conencted directly over
115 * RGMII in MAC-MAC mode
116 * In this case 1GBit full duplex and autoneg off
117 */
118#define PORT_SERIAL_CONTROL_VALUE ( \
119 MVGBE_FORCE_LINK_PASS | \
120 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
121 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
122 MVGBE_ADV_NO_FLOW_CTRL | \
123 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
124 MVGBE_FORCE_BP_MODE_NO_JAM | \
125 (1 << 9) /* Reserved bit has to be 1 */ | \
126 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
127 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
128 MVGBE_DTE_ADV_0 | \
129 MVGBE_MIIPHY_MAC_MODE | \
130 MVGBE_AUTO_NEG_NO_CHANGE | \
131 MVGBE_MAX_RX_PACKET_1552BYTE | \
132 MVGBE_CLR_EXT_LOOPBACK | \
133 MVGBE_SET_FULL_DUPLEX_MODE | \
134 MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
135 MVGBE_SET_GMII_SPEED_TO_1000 |\
136 MVGBE_SET_MII_SPEED_TO_100)
137
138#endif
Heiko Schocher731b9682011-03-08 10:53:51 +0100139
Holger Brunckf9454392012-07-05 05:05:03 +0000140#ifdef CONFIG_KM_PIGGY4_88E6061
141/*
142 * Some keymile boards like mgcoge3un have their PIGGY4 connected via
143 * an Marvell 88E6061 simple switch.
144 * In this case we have to change the default settings for the
145 * ethernet phy connected to the kirkwood.
146 * In this case 100MB full duplex and autoneg off
147 */
148#define PORT_SERIAL_CONTROL_VALUE ( \
149 MVGBE_FORCE_LINK_PASS | \
150 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
151 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
152 MVGBE_ADV_NO_FLOW_CTRL | \
153 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
154 MVGBE_FORCE_BP_MODE_NO_JAM | \
155 (1 << 9) /* Reserved bit has to be 1 */ | \
156 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
157 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
158 MVGBE_DTE_ADV_0 | \
159 MVGBE_MIIPHY_MAC_MODE | \
160 MVGBE_AUTO_NEG_NO_CHANGE | \
161 MVGBE_MAX_RX_PACKET_1552BYTE | \
162 MVGBE_CLR_EXT_LOOPBACK | \
163 MVGBE_SET_FULL_DUPLEX_MODE | \
164 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
165 MVGBE_SET_GMII_SPEED_TO_10_100 |\
166 MVGBE_SET_MII_SPEED_TO_100)
167#endif
168
Holger Brunckf9454392012-07-05 05:05:03 +0000169#ifdef CONFIG_KM_DISABLE_PCI
170#undef CONFIG_KIRKWOOD_PCIE_INIT
171#endif
Valentin Longchampb37f7722012-07-05 05:05:05 +0000172
Holger Brunck83b40c32011-06-16 18:11:15 +0530173#endif /* _CONFIG_KM_KIRKWOOD */