blob: 17a70a9ff6e73859a55bc89e0147dbe9de8e2157 [file] [log] [blame]
Stefan Roese8b7d1f02007-01-31 16:37:34 +01001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese8b7d1f02007-01-31 16:37:34 +01009 */
10
11/*
12 * pf5200.c - main board support/init for the esd pf5200.
13 */
14
15#include <common.h>
16#include <mpc5xxx.h>
17#include <pci.h>
18#include <command.h>
Ben Warren19403632008-08-31 10:03:22 -070019#include <netdev.h>
Stefan Roese8b7d1f02007-01-31 16:37:34 +010020
21#include "mt46v16m16-75.h"
22
23void init_power_switch(void);
24
25static void sdram_start(int hi_addr)
26{
27 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
28
29 /* unlock mode register */
30 *(vu_long *) MPC5XXX_SDRAM_CTRL =
31 SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
32 __asm__ volatile ("sync");
33
34 /* precharge all banks */
35 *(vu_long *) MPC5XXX_SDRAM_CTRL =
36 SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
37 __asm__ volatile ("sync");
38
39 /* set mode register: extended mode */
40 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
41 __asm__ volatile ("sync");
42
43 /* set mode register: reset DLL */
44 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
45 __asm__ volatile ("sync");
46
47 /* precharge all banks */
48 *(vu_long *) MPC5XXX_SDRAM_CTRL =
49 SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
50 __asm__ volatile ("sync");
51
52 /* auto refresh */
53 *(vu_long *) MPC5XXX_SDRAM_CTRL =
54 SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
55 __asm__ volatile ("sync");
56
57 /* set mode register */
58 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
59 __asm__ volatile ("sync");
60
61 /* normal operation */
62 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
63 __asm__ volatile ("sync");
64}
65
66/*
67 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
Stefan Roese8b7d1f02007-01-31 16:37:34 +010069 * is something else than 0x00000000.
70 */
71
Becky Bruce9973e3c2008-06-09 16:03:40 -050072phys_size_t initdram(int board_type)
Stefan Roese8b7d1f02007-01-31 16:37:34 +010073{
74 ulong dramsize = 0;
75 ulong test1, test2;
76
77 /* setup SDRAM chip selects */
78 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
79 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
80 __asm__ volatile ("sync");
81
82 /* setup config registers */
83 *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
84 *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
85 __asm__ volatile ("sync");
86
87 /* set tap delay */
88 *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
89 __asm__ volatile ("sync");
90
91 /* find RAM size using SDRAM CS0 only */
92 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
Stefan Roese8b7d1f02007-01-31 16:37:34 +010094 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
Stefan Roese8b7d1f02007-01-31 16:37:34 +010096
97 if (test1 > test2) {
98 sdram_start(0);
99 dramsize = test1;
100 } else {
101 dramsize = test2;
102 }
103
104 /* memory smaller than 1MB is impossible */
105 if (dramsize < (1 << 20))
106 dramsize = 0;
107
108 /* set SDRAM CS0 size according to the amount of RAM found */
109 if (dramsize > 0) {
110 *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
111 0x13 + __builtin_ffs(dramsize >> 20) - 1;
112 /* let SDRAM CS1 start right after CS0 */
113 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
114 } else {
115#if 0
116 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
117 /* let SDRAM CS1 start right after CS0 */
118 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
119#else
120 *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
121 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
122 /* let SDRAM CS1 start right after CS0 */
123 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
124#endif
125 }
126
127#if 0
128 /* find RAM size using SDRAM CS1 only */
129 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100131 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100133 sdram_start(0);
134#endif
135 /* set SDRAM CS1 size according to the amount of RAM found */
136
137 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
138
139 init_power_switch();
140 return (dramsize);
141}
142
143int checkboard(void)
144{
145 puts("Board: esd CPX CPU5200 (mecp5200)\n");
146 return 0;
147}
148
149void flash_preinit(void)
150{
151 /*
152 * Now, when we are in RAM, enable flash write
153 * access for detection process.
154 * Note that CS_BOOT cannot be cleared when
155 * executing in flash.
156 */
157 *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
158}
159
160void flash_afterinit(ulong size)
161{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 if (size == CONFIG_SYS_FLASH_SIZE) {
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100163 /* adjust mapping */
164 *(vu_long *) MPC5XXX_BOOTCS_START =
165 *(vu_long *) MPC5XXX_CS0_START =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 START_REG(CONFIG_SYS_BOOTCS_START | size);
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100167 *(vu_long *) MPC5XXX_BOOTCS_STOP =
168 *(vu_long *) MPC5XXX_CS0_STOP =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100170 }
171}
172
173#ifdef CONFIG_PCI
174static struct pci_controller hose;
175
176extern void pci_mpc5xxx_init(struct pci_controller *);
177
178void pci_init_board(void)
179{
180 pci_mpc5xxx_init(&hose);
181}
182#endif
183
Jon Loeliger77a31852007-07-10 10:39:10 -0500184#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100185
186#define GPIO_PSC1_4 0x01000000UL
187
188void init_ide_reset(void)
189{
190 debug("init_ide_reset\n");
191
192 /* Configure PSC1_4 as GPIO output for ATA reset */
193 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
194 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
195}
196
197void ide_set_reset(int idereset)
198{
199 debug("ide_reset(%d)\n", idereset);
200
201 if (idereset)
202 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
203 else
204 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
205}
Jon Loeliger77a31852007-07-10 10:39:10 -0500206#endif
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100207
208#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
209#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
210#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
211#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
212
213#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
214#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
215#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
216#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
217
218#define GPIO_WU6 0x40000000UL
219#define GPIO_USB0 0x00010000UL
220#define GPIO_USB9 0x08000000UL
221#define GPIO_USB9S 0x00080000UL
222
223void init_power_switch(void)
224{
225 debug("init_power_switch\n");
226
227 /* Configure GPIO_WU6 as GPIO output for ATA reset */
228 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
229 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
230 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
231 __asm__ volatile ("sync");
232
233 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
234 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
235 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
236 __asm__ volatile ("sync");
237
238 *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
239 *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
240 __asm__ volatile ("sync");
241
242 if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
243 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
244 __asm__ volatile ("sync");
245 }
246}
Ben Warren19403632008-08-31 10:03:22 -0700247
248int board_eth_init(bd_t *bis)
249{
250 return pci_eth_init(bis);
251}