blob: 37b7d99bd2ead63a9dcdf5dbe6da5be0aac24326 [file] [log] [blame]
Heiko Schocher4ce5a722009-07-20 09:59:37 +02001/*
2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family),
4 * and Kirkwood family.
5 *
6 * Based on:
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 *
9 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * ported from Linux to u-boot
15 * (C) Copyright 2009
16 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
17 *
18 */
19#include <common.h>
20#include <i2c.h>
21#include <asm/arch/kirkwood.h>
22#include <asm/errno.h>
23#include <asm/io.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
28#if defined(CONFIG_I2C_MUX)
29static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
30#endif
31
32/* Register defines */
33#define KW_I2C_REG_SLAVE_ADDR 0x00
34#define KW_I2C_REG_DATA 0x04
35#define KW_I2C_REG_CONTROL 0x08
36#define KW_I2C_REG_STATUS 0x0c
37#define KW_I2C_REG_BAUD 0x0c
38#define KW_I2C_REG_EXT_SLAVE_ADDR 0x10
39#define KW_I2C_REG_SOFT_RESET 0x1c
40
41#define KW_I2C_REG_CONTROL_ACK 0x00000004
42#define KW_I2C_REG_CONTROL_IFLG 0x00000008
43#define KW_I2C_REG_CONTROL_STOP 0x00000010
44#define KW_I2C_REG_CONTROL_START 0x00000020
45#define KW_I2C_REG_CONTROL_TWSIEN 0x00000040
46#define KW_I2C_REG_CONTROL_INTEN 0x00000080
47
48/* Ctlr status values */
49#define KW_I2C_STATUS_BUS_ERR 0x00
50#define KW_I2C_STATUS_MAST_START 0x08
51#define KW_I2C_STATUS_MAST_REPEAT_START 0x10
52#define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
53#define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
54#define KW_I2C_STATUS_MAST_WR_ACK 0x28
55#define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30
56#define KW_I2C_STATUS_MAST_LOST_ARB 0x38
57#define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
58#define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
59#define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50
60#define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
61#define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
62#define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
63#define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
64#define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
65#define KW_I2C_STATUS_NO_STATUS 0xf8
66
67/* Driver states */
68enum {
69 KW_I2C_STATE_INVALID,
70 KW_I2C_STATE_IDLE,
71 KW_I2C_STATE_WAITING_FOR_START_COND,
72 KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
73 KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
74 KW_I2C_STATE_WAITING_FOR_SLAVE_ACK,
75 KW_I2C_STATE_WAITING_FOR_SLAVE_DATA,
76};
77
78/* Driver actions */
79enum {
80 KW_I2C_ACTION_INVALID,
81 KW_I2C_ACTION_CONTINUE,
82 KW_I2C_ACTION_SEND_START,
83 KW_I2C_ACTION_SEND_ADDR_1,
84 KW_I2C_ACTION_SEND_ADDR_2,
85 KW_I2C_ACTION_SEND_DATA,
86 KW_I2C_ACTION_RCV_DATA,
87 KW_I2C_ACTION_RCV_DATA_STOP,
88 KW_I2C_ACTION_SEND_STOP,
89};
90
91/* defines to get compatible with Linux driver */
92#define IRQ_NONE 0x0
93#define IRQ_HANDLED 0x01
94
95#define I2C_M_TEN 0x01
96#define I2C_M_RD 0x02
97#define I2C_M_REV_DIR_ADDR 0x04;
98
99struct i2c_msg {
100 u32 addr;
101 u32 flags;
102 u8 *buf;
103 u32 len;
104};
105
106struct kirkwood_i2c_data {
107 int irq;
108 u32 state;
109 u32 action;
110 u32 aborting;
111 u32 cntl_bits;
112 void *reg_base;
113 u32 reg_base_p;
114 u32 reg_size;
115 u32 addr1;
116 u32 addr2;
117 u32 bytes_left;
118 u32 byte_posn;
119 u32 block;
120 int rc;
121 u32 freq_m;
122 u32 freq_n;
123 struct i2c_msg *msg;
124};
125
126static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data")));
127static struct kirkwood_i2c_data *drv_data = &__drv_data;
128static struct i2c_msg __i2c_msg __attribute__ ((section (".data")));
129static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg;
130
131/*
132 *****************************************************************************
133 *
134 * Finite State Machine & Interrupt Routines
135 *
136 *****************************************************************************
137 */
138
139static inline int abs(int n)
140{
141 if(n >= 0)
142 return n;
143 else
144 return n * -1;
145}
146
147static void kirkwood_calculate_speed(int speed)
148{
149 int calcspeed;
150 int diff;
151 int best_diff = CONFIG_SYS_TCLK;
152 int best_speed = 0;
153 int m, n;
154 int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256};
155
156 for (n = 0; n < 8; n++) {
157 for (m = 0; m < 16; m++) {
158 calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]);
159 diff = abs((speed - calcspeed));
160 if ( diff < best_diff) {
161 best_diff = diff;
162 best_speed = calcspeed;
163 drv_data->freq_m = m;
164 drv_data->freq_n = n;
165 }
166 }
167 }
168}
169
170/* Reset hardware and initialize FSM */
171static void
172kirkwood_i2c_hw_init(int speed, int slaveadd)
173{
174 drv_data->state = KW_I2C_STATE_IDLE;
175
176 kirkwood_calculate_speed(speed);
177 writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET);
178 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
179 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD);
180 writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR);
181 writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR);
182 writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP,
183 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
184}
185
186static void
187kirkwood_i2c_fsm(u32 status)
188{
189 /*
190 * If state is idle, then this is likely the remnants of an old
191 * operation that driver has given up on or the user has killed.
192 * If so, issue the stop condition and go to idle.
193 */
194 if (drv_data->state == KW_I2C_STATE_IDLE) {
195 drv_data->action = KW_I2C_ACTION_SEND_STOP;
196 return;
197 }
198
199 /* The status from the ctlr [mostly] tells us what to do next */
200 switch (status) {
201 /* Start condition interrupt */
202 case KW_I2C_STATUS_MAST_START: /* 0x08 */
203 case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
204 drv_data->action = KW_I2C_ACTION_SEND_ADDR_1;
205 drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
206 break;
207
208 /* Performing a write */
209 case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
210 if (drv_data->msg->flags & I2C_M_TEN) {
211 drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
212 drv_data->state =
213 KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
214 break;
215 }
216 /* FALLTHRU */
217 case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
218 case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
219 if ((drv_data->bytes_left == 0)
220 || (drv_data->aborting
221 && (drv_data->byte_posn != 0))) {
222 drv_data->action = KW_I2C_ACTION_SEND_STOP;
223 drv_data->state = KW_I2C_STATE_IDLE;
224 } else {
225 drv_data->action = KW_I2C_ACTION_SEND_DATA;
226 drv_data->state =
227 KW_I2C_STATE_WAITING_FOR_SLAVE_ACK;
228 drv_data->bytes_left--;
229 }
230 break;
231
232 /* Performing a read */
233 case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
234 if (drv_data->msg->flags & I2C_M_TEN) {
235 drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
236 drv_data->state =
237 KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
238 break;
239 }
240 /* FALLTHRU */
241 case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
242 if (drv_data->bytes_left == 0) {
243 drv_data->action = KW_I2C_ACTION_SEND_STOP;
244 drv_data->state = KW_I2C_STATE_IDLE;
245 break;
246 }
247 /* FALLTHRU */
248 case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
249 if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK)
250 drv_data->action = KW_I2C_ACTION_CONTINUE;
251 else {
252 drv_data->action = KW_I2C_ACTION_RCV_DATA;
253 drv_data->bytes_left--;
254 }
255 drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA;
256
257 if ((drv_data->bytes_left == 1) || drv_data->aborting)
258 drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK;
259 break;
260
261 case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
262 drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP;
263 drv_data->state = KW_I2C_STATE_IDLE;
264 break;
265
266 case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
267 case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
268 case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
269 /* Doesn't seem to be a device at other end */
270 drv_data->action = KW_I2C_ACTION_SEND_STOP;
271 drv_data->state = KW_I2C_STATE_IDLE;
272 drv_data->rc = -ENODEV;
273 break;
274
275 default:
276 printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, "
277 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
278 drv_data->state, status, drv_data->msg->addr,
279 drv_data->msg->flags);
280 drv_data->action = KW_I2C_ACTION_SEND_STOP;
281 kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
282 drv_data->rc = -EIO;
283 }
284}
285
286static void
287kirkwood_i2c_do_action(void)
288{
289 switch(drv_data->action) {
290 case KW_I2C_ACTION_CONTINUE:
291 writel(drv_data->cntl_bits,
292 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
293 break;
294
295 case KW_I2C_ACTION_SEND_START:
296 writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START,
297 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
298 break;
299
300 case KW_I2C_ACTION_SEND_ADDR_1:
301 writel(drv_data->addr1,
302 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
303 writel(drv_data->cntl_bits,
304 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
305 break;
306
307 case KW_I2C_ACTION_SEND_ADDR_2:
308 writel(drv_data->addr2,
309 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
310 writel(drv_data->cntl_bits,
311 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
312 break;
313
314 case KW_I2C_ACTION_SEND_DATA:
315 writel(drv_data->msg->buf[drv_data->byte_posn++],
316 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
317 writel(drv_data->cntl_bits,
318 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
319 break;
320
321 case KW_I2C_ACTION_RCV_DATA:
322 drv_data->msg->buf[drv_data->byte_posn++] =
323 readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
324 writel(drv_data->cntl_bits,
325 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
326 break;
327
328 case KW_I2C_ACTION_RCV_DATA_STOP:
329 drv_data->msg->buf[drv_data->byte_posn++] =
330 readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
331 drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
332 writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
333 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
334 drv_data->block = 0;
335 break;
336
337 case KW_I2C_ACTION_INVALID:
338 default:
339 printf("kirkwood_i2c_do_action: Invalid action: %d\n",
340 drv_data->action);
341 drv_data->rc = -EIO;
342 /* FALLTHRU */
343 case KW_I2C_ACTION_SEND_STOP:
344 drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
345 writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
346 CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
347 drv_data->block = 0;
348 break;
349 }
350}
351
352static int
353kirkwood_i2c_intr(void)
354{
355 u32 status;
356 u32 ctrl;
357 int rc = IRQ_NONE;
358
359 ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
360 while ((ctrl & KW_I2C_REG_CONTROL_IFLG) &&
361 (drv_data->rc == 0)) {
362 status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS);
363 kirkwood_i2c_fsm(status);
364 kirkwood_i2c_do_action();
365 rc = IRQ_HANDLED;
366 ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
367 udelay(1000);
368 }
369 return rc;
370}
371
372static void
373kirkwood_i2c_doio(struct i2c_msg *msg)
374{
375 int ret;
376
377 while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) {
378 /* poll Status register */
379 ret = kirkwood_i2c_intr();
380 if (ret == IRQ_NONE)
381 udelay(10);
382 }
383}
384
385static void
386kirkwood_i2c_prepare_for_io(struct i2c_msg *msg)
387{
388 u32 dir = 0;
389
390 drv_data->msg = msg;
391 drv_data->byte_posn = 0;
392 drv_data->bytes_left = msg->len;
393 drv_data->aborting = 0;
394 drv_data->rc = 0;
395 /* in u-boot we use no IRQs */
396 drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN;
397
398 if (msg->flags & I2C_M_RD)
399 dir = 1;
400 if (msg->flags & I2C_M_TEN) {
401 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
402 drv_data->addr2 = (u32)msg->addr & 0xff;
403 } else {
404 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
405 drv_data->addr2 = 0;
406 }
407 /* OK, no start it (from kirkwood_i2c_execute_msg())*/
408 drv_data->action = KW_I2C_ACTION_SEND_START;
409 drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND;
410 drv_data->block = 1;
411 kirkwood_i2c_do_action();
412}
413
414void
415i2c_init(int speed, int slaveadd)
416{
417 kirkwood_i2c_hw_init(speed, slaveadd);
418}
419
420int
421i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
422{
423 kirkwood_i2c_msg->buf = data;
424 kirkwood_i2c_msg->len = length;
425 kirkwood_i2c_msg->addr = dev;
426 kirkwood_i2c_msg->flags = I2C_M_RD;
427
428 kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
429 kirkwood_i2c_doio(kirkwood_i2c_msg);
430 return drv_data->rc;
431}
432
433int
434i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
435{
436 kirkwood_i2c_msg->buf = data;
437 kirkwood_i2c_msg->len = length;
438 kirkwood_i2c_msg->addr = dev;
439 kirkwood_i2c_msg->flags = 0;
440
441 kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
442 kirkwood_i2c_doio(kirkwood_i2c_msg);
443 return drv_data->rc;
444}
445
446int
447i2c_probe(uchar chip)
448{
449 return i2c_read(chip, 0, 0, NULL, 0);
450}
451
452int i2c_set_bus_num(unsigned int bus)
453{
454#if defined(CONFIG_I2C_MUX)
455 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
456 i2c_bus_num = bus;
457 } else {
458 int ret;
459
460 ret = i2x_mux_select_mux(bus);
461 if (ret)
462 return ret;
463 i2c_bus_num = 0;
464 }
465 i2c_bus_num_mux = bus;
466#else
467 if (bus > 0) {
468 return -1;
469 }
470
471 i2c_bus_num = bus;
472#endif
473 return 0;
474}
475
476unsigned int i2c_get_bus_num(void)
477{
478#if defined(CONFIG_I2C_MUX)
479 return i2c_bus_num_mux;
480#else
481 return i2c_bus_num;
482#endif
483}