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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Rick Chen56a4ca82017-12-26 13:55:54 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen56a4ca82017-12-26 13:55:54 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Pragnesh Patelbc8d12b2021-01-17 18:11:25 +053010#define RISCV_MMODE_TIMERBASE 0xe6000000
11#define RISCV_MMODE_TIMER_FREQ 60000000
12
13#define RISCV_SMODE_TIMER_FREQ 60000000
14
Rick Chen56a4ca82017-12-26 13:55:54 +080015/*
16 * CPU and Board Configuration Options
17 */
Rick Chen56a4ca82017-12-26 13:55:54 +080018
Rick Chen56a4ca82017-12-26 13:55:54 +080019/*
20 * Miscellaneous configurable options
21 */
Rick Chen56a4ca82017-12-26 13:55:54 +080022
Rick Chen56a4ca82017-12-26 13:55:54 +080023/*
24 * Physical Memory Map
25 */
Rick Chen56a4ca82017-12-26 13:55:54 +080026#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
27#define PHYS_SDRAM_1 \
28 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
29#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
30#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
31#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
32
33/*
34 * Serial console configuration
35 */
Rick Chen56a4ca82017-12-26 13:55:54 +080036#define CONFIG_SYS_NS16550_SERIAL
37#ifndef CONFIG_DM_SERIAL
38#define CONFIG_SYS_NS16550_REG_SIZE -4
39#endif
40#define CONFIG_SYS_NS16550_CLK 19660800
41
Rick Chen56a4ca82017-12-26 13:55:54 +080042/* Init Stack Pointer */
Rick Chen56a4ca82017-12-26 13:55:54 +080043
Rick Chenc038fd02018-05-29 11:04:23 +080044/* support JEDEC */
Rick Chenc038fd02018-05-29 11:04:23 +080045#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
46#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
47#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
Rick Chenc038fd02018-05-29 11:04:23 +080048
Rick Chenc038fd02018-05-29 11:04:23 +080049/* max number of memory banks */
50/*
51 * There are 4 banks supported for this Controller,
52 * but we have only 1 bank connected to flash on board
53*/
Rick Chenc038fd02018-05-29 11:04:23 +080054#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
55
56/* max number of sectors on one chip */
57#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
Rick Chenc038fd02018-05-29 11:04:23 +080058
Rick Chen56a4ca82017-12-26 13:55:54 +080059/* environments */
Rick Chen56a4ca82017-12-26 13:55:54 +080060
61/* SPI FLASH */
Rick Chen56a4ca82017-12-26 13:55:54 +080062
63/*
64 * For booting Linux, the board info and command line data
65 * have to be in the first 16 MB of memory, since this is
66 * the maximum mapped by the Linux kernel during initialization.
67 */
68
69/* Initial Memory map for Linux*/
70#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
71/* Increase max gunzip size */
Rick Chen56a4ca82017-12-26 13:55:54 +080072
Leo Yu-Chi Liang666da852021-11-04 09:53:26 +080073/* Support autoboot from RAM (kernel image is loaded via debug port) */
74#define KERNEL_IMAGE_ADDR "0x2000000 "
75#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
76 "ram "
77#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
78 "bootcmd_ram=" \
79 "booti " \
80 KERNEL_IMAGE_ADDR \
81 "- $fdtcontroladdr\0"
82
Alexander Graf0979f7c2018-04-23 07:59:49 +020083/* When we use RAM as ENV */
Alexander Graf0979f7c2018-04-23 07:59:49 +020084
85/* Enable distro boot */
86#define BOOT_TARGET_DEVICES(func) \
87 func(MMC, mmc, 0) \
Leo Yu-Chi Liang666da852021-11-04 09:53:26 +080088 func(DHCP, dhcp, na) \
89 func(RAM, ram, na)
Alexander Graf0979f7c2018-04-23 07:59:49 +020090#include <config_distro_bootcmd.h>
91
92#define CONFIG_EXTRA_ENV_SETTINGS \
93 "kernel_addr_r=0x00080000\0" \
94 "pxefile_addr_r=0x01f00000\0" \
95 "scriptaddr=0x01f00000\0" \
96 "fdt_addr_r=0x02000000\0" \
97 "ramdisk_addr_r=0x02800000\0" \
98 BOOTENV
99
Rick Chen56a4ca82017-12-26 13:55:54 +0800100#endif /* __CONFIG_H */