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Wolfgang Denk265817c2005-09-25 00:53:22 +02001/* Memory sub-system initialization code */
2
3#include <config.h>
Daniel Schwierzeck76ada5f2015-12-21 16:35:14 +01004#include <mach/au1x00.h>
Wolfgang Denk265817c2005-09-25 00:53:22 +02005#include <asm/regdef.h>
Wolfgang Denk265817c2005-09-25 00:53:22 +02006#include <asm/mipsregs.h>
7
8#define AU1500_SYS_ADDR 0xB1900000
9#define sys_endian 0x0038
10#define CP0_Config0 $16
11#define MEM_1MS ((396000000/1000000) * 1000)
12
13 .text
14 .set noreorder
15 .set mips32
16
Shinya Kuribayashi2e4a6e32007-10-27 15:00:24 +090017 .globl lowlevel_init
18lowlevel_init:
Wolfgang Denk265817c2005-09-25 00:53:22 +020019 /*
20 * Step 1) Establish CPU endian mode.
21 * NOTE: A fair amount of code is necessary on the Pb1000 to
22 * obtain the value of Switch S8.1 which is used to determine
23 * endian at run-time.
24 */
25
26 /* RCE1 */
27 li t0, MEM_STCFG1
28 li t1, 0x00000083
29 sw t1, 0(t0)
30
31 li t0, MEM_STTIME1
32 li t1, 0x33030A10
33 sw t1, 0(t0)
34
35 li t0, MEM_STADDR1
36 li t1, 0x11803E40
37 sw t1, 0(t0)
38
39 /* Set DSTRB bits so switch will read correctly */
40 li t1, 0xBE00000C
41 lw t2, 0(t1)
42 or t2, t2, 0x00000300
43 sw t2, 0(t1)
44
45 /* Check switch setting */
46 li t1, 0xBE000014
47 lw t2, 0(t1)
48 and t2, t2, 0x00000100
49 bne t2, zero, big_endian
50 nop
51
52little_endian:
53
54 /* Change Au1 core to little endian */
55 li t0, AU1500_SYS_ADDR
56 li t1, 1
57 sw t1, sys_endian(t0)
58 mfc0 t2, CP0_CONFIG
59 mtc0 t2, CP0_CONFIG
60 nop
61 nop
62
63 /* Big Endian is default so nothing to do but fall through */
64
65big_endian:
66
67 /*
68 * Step 2) Establish Status Register
69 * (set BEV, clear ERL, clear EXL, clear IE)
70 */
71 li t1, 0x00400000
72 mtc0 t1, CP0_STATUS
73
74 /*
75 * Step 3) Establish CP0 Config0
76 * (set OD, set K0=3)
77 */
78 li t1, 0x00080003
79 mtc0 t1, CP0_CONFIG
80
81 /*
82 * Step 4) Disable Watchpoint facilities
83 */
84 li t1, 0x00000000
85 mtc0 t1, CP0_WATCHLO
86 mtc0 t1, CP0_IWATCHLO
87 /*
88 * Step 5) Disable the performance counters
89 */
90 mtc0 zero, CP0_PERFORMANCE
91 nop
92
93 /*
94 * Step 6) Establish EJTAG Debug register
95 */
96 mtc0 zero, CP0_DEBUG
97 nop
98
99 /*
100 * Step 7) Establish Cause
101 * (set IV bit)
102 */
103 li t1, 0x00800000
104 mtc0 t1, CP0_CAUSE
105
106 /* Establish Wired (and Random) */
107 mtc0 zero, CP0_WIRED
108 nop
109
110 /* First setup pll:s to make serial work ok */
111 /* We have a 12 MHz crystal */
112 li t0, SYS_CPUPLL
113 li t1, 0x21 /* 396 MHz */
114 sw t1, 0(t0)
115 sync
116 nop
117 nop
118
119 /* wait 1mS for clocks to settle */
120 li t1, MEM_1MS
1211: add t1, -1
122 bne t1, zero, 1b
123 nop
124 /* Setup AUX PLL */
125 li t0, SYS_AUXPLL
126 li t1, 8 /* 96 MHz */
127 sw t1, 0(t0) /* aux pll */
128 sync
129
130 /* Static memory controller */
131
132 /* RCE0 8MB AMD29D323 Flash */
133 li t0, MEM_STCFG0
134 li t1, 0x00001403
135 sw t1, 0(t0)
136
137 li t0, MEM_STTIME0
138 li t1, 0xFFFFFFDD
139 sw t1, 0(t0)
140
141 li t0, MEM_STADDR0
142 li t1, 0x11F83FE0
143 sw t1, 0(t0)
144
145 /* RCE1 CPLD Board Logic */
146 li t0, MEM_STCFG1
147 li t1, 0x00000083
148 sw t1, 0(t0)
149
150 li t0, MEM_STTIME1
151 li t1, 0x33030A10
152 sw t1, 0(t0)
153
154 li t0, MEM_STADDR1
155 li t1, 0x11803E40
156 sw t1, 0(t0)
157
158 /* RCE2 CPLD Board Logic */
159 li t0, MEM_STCFG2
160 li t1, 0x00000004
161 sw t1, 0(t0)
162
163 li t0, MEM_STTIME2
164 li t1, 0x08061908
165 sw t1, 0(t0)
166
167 li t0, MEM_STADDR2
168 li t1, 0x12A03FC0
169 sw t1, 0(t0)
170
171 /* RCE3 PCMCIA 250ns */
172 li t0, MEM_STCFG3
173 li t1, 0x00000002
174 sw t1, 0(t0)
175
176 li t0, MEM_STTIME3
177 li t1, 0x280E3E07
178 sw t1, 0(t0)
179
180 li t0, MEM_STADDR3
181 li t1, 0x10000000
182 sw t1, 0(t0)
183
184 sync
185
186 /* Set peripherals to a known state */
187 li t0, IC0_CFG0CLR
188 li t1, 0xFFFFFFFF
189 sw t1, 0(t0)
190
191 li t0, IC0_CFG0CLR
192 sw t1, 0(t0)
193
194 li t0, IC0_CFG1CLR
195 sw t1, 0(t0)
196
197 li t0, IC0_CFG2CLR
198 sw t1, 0(t0)
199
200 li t0, IC0_SRCSET
201 sw t1, 0(t0)
202
203 li t0, IC0_ASSIGNSET
204 sw t1, 0(t0)
205
206 li t0, IC0_WAKECLR
207 sw t1, 0(t0)
208
209 li t0, IC0_RISINGCLR
210 sw t1, 0(t0)
211
212 li t0, IC0_FALLINGCLR
213 sw t1, 0(t0)
214
215 li t0, IC0_TESTBIT
216 li t1, 0x00000000
217 sw t1, 0(t0)
218 sync
219
220 li t0, IC1_CFG0CLR
221 li t1, 0xFFFFFFFF
222 sw t1, 0(t0)
223
224 li t0, IC1_CFG0CLR
225 sw t1, 0(t0)
226
227 li t0, IC1_CFG1CLR
228 sw t1, 0(t0)
229
230 li t0, IC1_CFG2CLR
231 sw t1, 0(t0)
232
233 li t0, IC1_SRCSET
234 sw t1, 0(t0)
235
236 li t0, IC1_ASSIGNSET
237 sw t1, 0(t0)
238
239 li t0, IC1_WAKECLR
240 sw t1, 0(t0)
241
242 li t0, IC1_RISINGCLR
243 sw t1, 0(t0)
244
245 li t0, IC1_FALLINGCLR
246 sw t1, 0(t0)
247
248 li t0, IC1_TESTBIT
249 li t1, 0x00000000
250 sw t1, 0(t0)
251 sync
252
253 li t0, SYS_FREQCTRL0
254 li t1, 0x00000000
255 sw t1, 0(t0)
256
257 li t0, SYS_FREQCTRL1
258 li t1, 0x00000000
259 sw t1, 0(t0)
260
261 li t0, SYS_CLKSRC
262 li t1, 0x00000000
263 sw t1, 0(t0)
264
265 li t0, SYS_PININPUTEN
266 li t1, 0x00000000
267 sw t1, 0(t0)
268 sync
269
270 li t0, 0xB1100100
271 li t1, 0x00000000
272 sw t1, 0(t0)
273
274 li t0, 0xB1400100
275 li t1, 0x00000000
276 sw t1, 0(t0)
277
278
279 li t0, SYS_WAKEMSK
280 li t1, 0x00000000
281 sw t1, 0(t0)
282
283 li t0, SYS_WAKESRC
284 li t1, 0x00000000
285 sw t1, 0(t0)
286
287 /* wait 1mS before setup */
288 li t1, MEM_1MS
2891: add t1, -1
290 bne t1, zero, 1b
291 nop
292
293 /*
294 * Skip memory setup if we are running from memory
295 */
296 li t0, 0x90000000
297 sub t0, ra, t0
298 bltz t0, skip_memsetup
299 nop
300
301 /*
302 * SDCS0 - Not used, for SMROM
303 * SDCS1 - 32MB Micron 48LCBM16A2
304 * SDCS2 - 32MB Micron 48LCBM16A2
305 */
306 li t0, MEM_SDMODE0
307 li t1, 0x00000000
308 sw t1, 0(t0)
309
310 li t0, MEM_SDMODE1
311 li t1, 0x00552229
312 sw t1, 0(t0)
313
314 li t0, MEM_SDMODE2
315 li t1, 0x00552229
316 sw t1, 0(t0)
317
318 li t0, MEM_SDADDR0
319 li t1, 0x00000000
320 sw t1, 0(t0)
321
322 li t0, MEM_SDADDR1
323 li t1, 0x001003F8
324 sw t1, 0(t0)
325
326 li t0, MEM_SDADDR2
327 li t1, 0x001023F8
328 sw t1, 0(t0)
329
330 sync
331
332 li t0, MEM_SDREFCFG
333 li t1, 0x74000c30 /* Disable */
334 sw t1, 0(t0)
335 sync
336
337 li t0, MEM_SDPRECMD
338 sw zero, 0(t0)
339 sync
340
341 li t0, MEM_SDAUTOREF
342 sw zero, 0(t0)
343 sync
344 sw zero, 0(t0)
345 sync
346
347 li t0, MEM_SDREFCFG
348 li t1, 0x76000c30 /* Enable */
349 sw t1, 0(t0)
350 sync
351
352 li t0, MEM_SDWRMD0
353 li t1, 0x00000023
354 sw t1, 0(t0)
355 sync
356
357 li t0, MEM_SDWRMD1
358 li t1, 0x00000023
359 sw t1, 0(t0)
360 sync
361
362 li t0, MEM_SDWRMD2
363 li t1, 0x00000023
364 sw t1, 0(t0)
365 sync
366
367 /* wait 1mS after setup */
368 li t1, MEM_1MS
3691: add t1, -1
370 bne t1, zero, 1b
371 nop
372
373skip_memsetup:
374
375 li t0, SYS_PINFUNC
376 li t1, 0/*0x00008080*/
377 sw t1, 0(t0)
378
379 /*
380 li t0, SYS_TRIOUTCLR
381 li t1, 0x00001FFF
382 sw t1, 0(t0)
383
384 li t0, SYS_OUTPUTCLR
385 li t1, 0x00008000
386 sw t1, 0(t0)
387 */
388 sync
389
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900390 jr ra
Wolfgang Denk265817c2005-09-25 00:53:22 +0200391 nop