blob: 7993c1a09955af490d10ac846981d3dab8a3bc88 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +000010 */
11
12/*
13 * PCI routines
14 */
15
16#include <common.h>
Simon Glass0098e172014-04-10 20:01:30 -060017#include <bootretry.h>
Simon Glass18d66532014-04-10 20:01:25 -060018#include <cli.h>
wdenkc6097192002-11-03 00:24:07 +000019#include <command.h>
Simon Glass24b852a2015-11-08 23:47:45 -070020#include <console.h>
Simon Glasscab24b32015-11-26 19:51:29 -070021#include <dm.h>
wdenkc6097192002-11-03 00:24:07 +000022#include <asm/processor.h>
23#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000024#include <pci.h>
25
Simon Glass07a58872015-11-26 19:51:20 -070026struct pci_reg_info {
27 const char *name;
28 enum pci_size_t size;
29 u8 offset;
30};
31
Simon Glass72ef5b62015-11-26 19:51:26 -070032static int pci_byte_size(enum pci_size_t size)
Simon Glass07a58872015-11-26 19:51:20 -070033{
34 switch (size) {
35 case PCI_SIZE_8:
Simon Glass72ef5b62015-11-26 19:51:26 -070036 return 1;
Simon Glass07a58872015-11-26 19:51:20 -070037 case PCI_SIZE_16:
Simon Glass72ef5b62015-11-26 19:51:26 -070038 return 2;
Simon Glass07a58872015-11-26 19:51:20 -070039 case PCI_SIZE_32:
40 default:
Simon Glass72ef5b62015-11-26 19:51:26 -070041 return 4;
Simon Glass07a58872015-11-26 19:51:20 -070042 }
43}
44
Simon Glass72ef5b62015-11-26 19:51:26 -070045static int pci_field_width(enum pci_size_t size)
46{
47 return pci_byte_size(size) * 2;
48}
49
Simon Glasscab24b32015-11-26 19:51:29 -070050#ifdef CONFIG_DM_PCI
51static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
52{
53 for (; regs->name; regs++) {
54 unsigned long val;
55
56 dm_pci_read_config(dev, regs->offset, &val, regs->size);
57 printf(" %s =%*s%#.*lx\n", regs->name,
58 (int)(28 - strlen(regs->name)), "",
59 pci_field_width(regs->size), val);
60 }
61}
62#else
Simon Glass07a58872015-11-26 19:51:20 -070063static unsigned long pci_read_config(pci_dev_t dev, int offset,
64 enum pci_size_t size)
65{
66 u32 val32;
67 u16 val16;
68 u8 val8;
69
70 switch (size) {
71 case PCI_SIZE_8:
72 pci_read_config_byte(dev, offset, &val8);
73 return val8;
74 case PCI_SIZE_16:
75 pci_read_config_word(dev, offset, &val16);
76 return val16;
77 case PCI_SIZE_32:
78 default:
79 pci_read_config_dword(dev, offset, &val32);
80 return val32;
81 }
82}
83
84static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
85{
86 for (; regs->name; regs++) {
87 printf(" %s =%*s%#.*lx\n", regs->name,
88 (int)(28 - strlen(regs->name)), "",
89 pci_field_width(regs->size),
90 pci_read_config(dev, regs->offset, regs->size));
91 }
92}
Simon Glasscab24b32015-11-26 19:51:29 -070093#endif
Simon Glass07a58872015-11-26 19:51:20 -070094
Yehuda Yitschake5f96a82016-12-01 17:14:18 +020095#ifdef CONFIG_DM_PCI
96int pci_bar_show(struct udevice *dev)
97{
98 u8 header_type;
99 int bar_cnt, bar_id, mem_type;
100 bool is_64, is_io;
101 u32 base_low, base_high;
102 u32 size_low, size_high;
103 u64 base, size;
104 u32 reg_addr;
105 int prefetchable;
106
107 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
108
109 if (header_type == PCI_HEADER_TYPE_CARDBUS) {
110 printf("CardBus doesn't support BARs\n");
111 return -ENOSYS;
112 }
113
114 bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
115
116 printf("ID Base Size Width Type\n");
117 printf("----------------------------------------------------------\n");
118
119 bar_id = 0;
120 reg_addr = PCI_BASE_ADDRESS_0;
121 while (bar_cnt) {
122 dm_pci_read_config32(dev, reg_addr, &base_low);
123 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
124 dm_pci_read_config32(dev, reg_addr, &size_low);
125 dm_pci_write_config32(dev, reg_addr, base_low);
126 reg_addr += 4;
127
128 base = base_low & ~0xf;
129 size = size_low & ~0xf;
130 base_high = 0x0;
131 size_high = 0xffffffff;
132 is_64 = 0;
133 prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
134 is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
135 mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
136
137 if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
138 dm_pci_read_config32(dev, reg_addr, &base_high);
139 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
140 dm_pci_read_config32(dev, reg_addr, &size_high);
141 dm_pci_write_config32(dev, reg_addr, base_high);
142 bar_cnt--;
143 reg_addr += 4;
144 is_64 = 1;
145 }
146
147 base = base | ((u64)base_high << 32);
148 size = size | ((u64)size_high << 32);
149
150 if ((!is_64 && size_low) || (is_64 && size)) {
151 size = ~size + 1;
152 printf(" %d %#016llx %#016llx %d %s %s\n",
153 bar_id, base, size, is_64 ? 64 : 32,
154 is_io ? "I/O" : "MEM",
155 prefetchable ? "Prefetchable" : "");
156 }
157
158 bar_id++;
159 bar_cnt--;
160 }
161
162 return 0;
163}
164#endif
165
Simon Glass07a58872015-11-26 19:51:20 -0700166static struct pci_reg_info regs_start[] = {
167 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
168 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
169 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
170 { "status register", PCI_SIZE_16, PCI_STATUS },
171 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
172 {},
173};
174
175static struct pci_reg_info regs_rest[] = {
176 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
177 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
178 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
179 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
180 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
181 { "BIST", PCI_SIZE_8, PCI_BIST },
182 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
183 {},
184};
185
186static struct pci_reg_info regs_normal[] = {
187 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
188 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
189 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
190 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
191 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
192 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
193 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
194 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
195 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
196 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
197 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
198 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
199 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
200 {},
201};
202
203static struct pci_reg_info regs_bridge[] = {
204 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
205 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
206 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
207 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
208 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
209 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
210 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
211 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
212 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
213 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
214 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
215 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
216 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
217 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
218 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
219 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
220 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
221 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
222 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
223 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
224 {},
225};
226
227static struct pci_reg_info regs_cardbus[] = {
228 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
229 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
230 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
231 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
232 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
233 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
234 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
235 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
236 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
237 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
238 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
239 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
240 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
241 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
242 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
243 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
244 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
245 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
246 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
247 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
248 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
249 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
250 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
251 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
252 {},
253};
254
Simon Glassc2be0702015-11-26 19:51:25 -0700255/**
256 * pci_header_show() - Show the header of the specified PCI device.
wdenkc6097192002-11-03 00:24:07 +0000257 *
Simon Glassc2be0702015-11-26 19:51:25 -0700258 * @dev: Bus+Device+Function number
wdenkc6097192002-11-03 00:24:07 +0000259 */
Simon Glasscab24b32015-11-26 19:51:29 -0700260#ifdef CONFIG_DM_PCI
261void pci_header_show(struct udevice *dev)
262#else
wdenkc6097192002-11-03 00:24:07 +0000263void pci_header_show(pci_dev_t dev)
Simon Glasscab24b32015-11-26 19:51:29 -0700264#endif
wdenkc6097192002-11-03 00:24:07 +0000265{
Simon Glasscab24b32015-11-26 19:51:29 -0700266#ifdef CONFIG_DM_PCI
267 unsigned long class, header_type;
268
269 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
270 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
271#else
Simon Glass07a58872015-11-26 19:51:20 -0700272 u8 class, header_type;
wdenkc6097192002-11-03 00:24:07 +0000273
Simon Glass49f835f2015-11-26 19:51:24 -0700274 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
wdenkc6097192002-11-03 00:24:07 +0000275 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
Simon Glasscab24b32015-11-26 19:51:29 -0700276#endif
Simon Glass07a58872015-11-26 19:51:20 -0700277 pci_show_regs(dev, regs_start);
Simon Glasscab24b32015-11-26 19:51:29 -0700278 printf(" class code = 0x%.2x (%s)\n", (int)class,
Simon Glass07a58872015-11-26 19:51:20 -0700279 pci_class_str(class));
280 pci_show_regs(dev, regs_rest);
wdenkc6097192002-11-03 00:24:07 +0000281
wdenk7c7a23b2002-12-07 00:20:59 +0000282 switch (header_type & 0x03) {
283 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
Simon Glass07a58872015-11-26 19:51:20 -0700284 pci_show_regs(dev, regs_normal);
wdenk7c7a23b2002-12-07 00:20:59 +0000285 break;
wdenk7c7a23b2002-12-07 00:20:59 +0000286 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
Simon Glass07a58872015-11-26 19:51:20 -0700287 pci_show_regs(dev, regs_bridge);
wdenk7c7a23b2002-12-07 00:20:59 +0000288 break;
wdenk7c7a23b2002-12-07 00:20:59 +0000289 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
Simon Glass07a58872015-11-26 19:51:20 -0700290 pci_show_regs(dev, regs_cardbus);
wdenk7c7a23b2002-12-07 00:20:59 +0000291 break;
wdenk8bde7f72003-06-27 21:31:46 +0000292
wdenk7c7a23b2002-12-07 00:20:59 +0000293 default:
294 printf("unknown header\n");
wdenk8bde7f72003-06-27 21:31:46 +0000295 break;
wdenkc6097192002-11-03 00:24:07 +0000296 }
wdenkc6097192002-11-03 00:24:07 +0000297}
298
Simon Glassc4f32bb2015-11-26 19:51:28 -0700299void pciinfo_header(int busnum, bool short_listing)
300{
301 printf("Scanning PCI devices on bus %d\n", busnum);
302
303 if (short_listing) {
304 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
305 printf("_____________________________________________________________\n");
306 }
307}
308
Simon Glasscab24b32015-11-26 19:51:29 -0700309#ifdef CONFIG_DM_PCI
310/**
311 * pci_header_show_brief() - Show the short-form PCI device header
312 *
313 * Reads and prints the header of the specified PCI device in short form.
314 *
315 * @dev: PCI device to show
316 */
317static void pci_header_show_brief(struct udevice *dev)
318{
319 ulong vendor, device;
320 ulong class, subclass;
321
322 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
323 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
324 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
325 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
326
327 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
328 vendor, device,
329 pci_class_str(class), subclass);
330}
331
332static void pciinfo(struct udevice *bus, bool short_listing)
333{
334 struct udevice *dev;
335
336 pciinfo_header(bus->seq, short_listing);
337
338 for (device_find_first_child(bus, &dev);
339 dev;
340 device_find_next_child(&dev)) {
341 struct pci_child_platdata *pplat;
342
343 pplat = dev_get_parent_platdata(dev);
344 if (short_listing) {
345 printf("%02x.%02x.%02x ", bus->seq,
346 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
347 pci_header_show_brief(dev);
348 } else {
349 printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq,
350 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
351 pci_header_show(dev);
352 }
353 }
354}
355
356#else
357
Simon Glassc2be0702015-11-26 19:51:25 -0700358/**
359 * pci_header_show_brief() - Show the short-form PCI device header
Simon Glass49f835f2015-11-26 19:51:24 -0700360 *
Simon Glassc2be0702015-11-26 19:51:25 -0700361 * Reads and prints the header of the specified PCI device in short form.
Simon Glass49f835f2015-11-26 19:51:24 -0700362 *
Simon Glassc2be0702015-11-26 19:51:25 -0700363 * @dev: Bus+Device+Function number
Simon Glass49f835f2015-11-26 19:51:24 -0700364 */
365void pci_header_show_brief(pci_dev_t dev)
366{
367 u16 vendor, device;
368 u8 class, subclass;
369
370 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
371 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
372 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
373 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
374
375 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
376 vendor, device,
377 pci_class_str(class), subclass);
378}
379
Simon Glassc2be0702015-11-26 19:51:25 -0700380/**
381 * pciinfo() - Show a list of devices on the PCI bus
Simon Glass49f835f2015-11-26 19:51:24 -0700382 *
Simon Glassc2be0702015-11-26 19:51:25 -0700383 * Show information about devices on PCI bus. Depending on @short_pci_listing
384 * the output will be more or less exhaustive.
Simon Glass49f835f2015-11-26 19:51:24 -0700385 *
Simon Glassc2be0702015-11-26 19:51:25 -0700386 * @bus_num: The number of the bus to be scanned
387 * @short_pci_listing: true to use short form, showing only a brief header
388 * for each device
Simon Glass49f835f2015-11-26 19:51:24 -0700389 */
390void pciinfo(int bus_num, int short_pci_listing)
391{
392 struct pci_controller *hose = pci_bus_to_hose(bus_num);
Simon Glassc2be0702015-11-26 19:51:25 -0700393 int device;
394 int function;
395 unsigned char header_type;
396 unsigned short vendor_id;
Simon Glass49f835f2015-11-26 19:51:24 -0700397 pci_dev_t dev;
398 int ret;
399
400 if (!hose)
401 return;
402
Simon Glassc4f32bb2015-11-26 19:51:28 -0700403 pciinfo_header(bus_num, short_pci_listing);
Simon Glass49f835f2015-11-26 19:51:24 -0700404
Simon Glassc2be0702015-11-26 19:51:25 -0700405 for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
406 header_type = 0;
407 vendor_id = 0;
408 for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
409 function++) {
Simon Glass49f835f2015-11-26 19:51:24 -0700410 /*
411 * If this is not a multi-function device, we skip
412 * the rest.
413 */
Simon Glassc2be0702015-11-26 19:51:25 -0700414 if (function && !(header_type & 0x80))
Simon Glass49f835f2015-11-26 19:51:24 -0700415 break;
416
Simon Glassc2be0702015-11-26 19:51:25 -0700417 dev = PCI_BDF(bus_num, device, function);
Simon Glass49f835f2015-11-26 19:51:24 -0700418
419 if (pci_skip_dev(hose, dev))
420 continue;
421
422 ret = pci_read_config_word(dev, PCI_VENDOR_ID,
Simon Glassc2be0702015-11-26 19:51:25 -0700423 &vendor_id);
Simon Glass49f835f2015-11-26 19:51:24 -0700424 if (ret)
425 goto error;
Simon Glassc2be0702015-11-26 19:51:25 -0700426 if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
Simon Glass49f835f2015-11-26 19:51:24 -0700427 continue;
428
Simon Glassc2be0702015-11-26 19:51:25 -0700429 if (!function) {
Simon Glass49f835f2015-11-26 19:51:24 -0700430 pci_read_config_byte(dev, PCI_HEADER_TYPE,
Simon Glassc2be0702015-11-26 19:51:25 -0700431 &header_type);
Simon Glass49f835f2015-11-26 19:51:24 -0700432 }
433
434 if (short_pci_listing) {
Simon Glassc2be0702015-11-26 19:51:25 -0700435 printf("%02x.%02x.%02x ", bus_num, device,
436 function);
Simon Glass49f835f2015-11-26 19:51:24 -0700437 pci_header_show_brief(dev);
438 } else {
439 printf("\nFound PCI device %02x.%02x.%02x:\n",
Simon Glassc2be0702015-11-26 19:51:25 -0700440 bus_num, device, function);
Simon Glass49f835f2015-11-26 19:51:24 -0700441 pci_header_show(dev);
442 }
443 }
444 }
445
446 return;
447error:
448 printf("Cannot read bus configuration: %d\n", ret);
449}
Simon Glasscab24b32015-11-26 19:51:29 -0700450#endif
Simon Glass49f835f2015-11-26 19:51:24 -0700451
Simon Glassc2be0702015-11-26 19:51:25 -0700452/**
453 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
454 *
455 * @name: Device string in the form "bus.device.function" where each is in hex
456 * @return encoded pci_dev_t or -1 if the string was invalid
wdenkc6097192002-11-03 00:24:07 +0000457 */
Simon Glassc2be0702015-11-26 19:51:25 -0700458static pci_dev_t get_pci_dev(char *name)
wdenkc6097192002-11-03 00:24:07 +0000459{
460 char cnum[12];
461 int len, i, iold, n;
462 int bdfs[3] = {0,0,0};
463
464 len = strlen(name);
465 if (len > 8)
466 return -1;
467 for (i = 0, iold = 0, n = 0; i < len; i++) {
468 if (name[i] == '.') {
469 memcpy(cnum, &name[iold], i - iold);
470 cnum[i - iold] = '\0';
471 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
472 iold = i + 1;
473 }
474 }
475 strcpy(cnum, &name[iold]);
476 if (n == 0)
477 n = 1;
478 bdfs[n] = simple_strtoul(cnum, NULL, 16);
Simon Glassc2be0702015-11-26 19:51:25 -0700479
wdenkc6097192002-11-03 00:24:07 +0000480 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
481}
482
Simon Glasscab24b32015-11-26 19:51:29 -0700483#ifdef CONFIG_DM_PCI
484static int pci_cfg_display(struct udevice *dev, ulong addr,
485 enum pci_size_t size, ulong length)
486#else
Simon Glass72ef5b62015-11-26 19:51:26 -0700487static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
488 ulong length)
Simon Glasscab24b32015-11-26 19:51:29 -0700489#endif
wdenkc6097192002-11-03 00:24:07 +0000490{
491#define DISP_LINE_LEN 16
492 ulong i, nbytes, linebytes;
Simon Glass72ef5b62015-11-26 19:51:26 -0700493 int byte_size;
wdenkc6097192002-11-03 00:24:07 +0000494 int rc = 0;
495
Simon Glass72ef5b62015-11-26 19:51:26 -0700496 byte_size = pci_byte_size(size);
wdenkc6097192002-11-03 00:24:07 +0000497 if (length == 0)
Simon Glass72ef5b62015-11-26 19:51:26 -0700498 length = 0x40 / byte_size; /* Standard PCI config space */
wdenkc6097192002-11-03 00:24:07 +0000499
500 /* Print the lines.
501 * once, and all accesses are with the specified bus width.
502 */
Simon Glass72ef5b62015-11-26 19:51:26 -0700503 nbytes = length * byte_size;
wdenkc6097192002-11-03 00:24:07 +0000504 do {
wdenkc6097192002-11-03 00:24:07 +0000505 printf("%08lx:", addr);
Simon Glass72ef5b62015-11-26 19:51:26 -0700506 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
507 for (i = 0; i < linebytes; i += byte_size) {
508 unsigned long val;
509
Simon Glasscab24b32015-11-26 19:51:29 -0700510#ifdef CONFIG_DM_PCI
511 dm_pci_read_config(dev, addr, &val, size);
512#else
Simon Glass72ef5b62015-11-26 19:51:26 -0700513 val = pci_read_config(bdf, addr, size);
Simon Glasscab24b32015-11-26 19:51:29 -0700514#endif
Simon Glass72ef5b62015-11-26 19:51:26 -0700515 printf(" %0*lx", pci_field_width(size), val);
516 addr += byte_size;
wdenkc6097192002-11-03 00:24:07 +0000517 }
518 printf("\n");
519 nbytes -= linebytes;
520 if (ctrlc()) {
521 rc = 1;
522 break;
523 }
524 } while (nbytes > 0);
525
526 return (rc);
527}
528
Simon Glasscab24b32015-11-26 19:51:29 -0700529#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000530static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
531{
532 if (size == 4) {
533 pci_write_config_dword(bdf, addr, value);
534 }
535 else if (size == 2) {
536 ushort val = value & 0xffff;
537 pci_write_config_word(bdf, addr, val);
538 }
539 else {
540 u_char val = value & 0xff;
541 pci_write_config_byte(bdf, addr, val);
542 }
543 return 0;
544}
Simon Glasscab24b32015-11-26 19:51:29 -0700545#endif
wdenkc6097192002-11-03 00:24:07 +0000546
Simon Glasscab24b32015-11-26 19:51:29 -0700547#ifdef CONFIG_DM_PCI
548static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
Simon Glass72ef5b62015-11-26 19:51:26 -0700549 ulong value, int incrflag)
Simon Glasscab24b32015-11-26 19:51:29 -0700550#else
551static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
552 int incrflag)
553#endif
wdenkc6097192002-11-03 00:24:07 +0000554{
555 ulong i;
556 int nbytes;
Simon Glass72ef5b62015-11-26 19:51:26 -0700557 ulong val;
wdenkc6097192002-11-03 00:24:07 +0000558
559 /* Print the address, followed by value. Then accept input for
560 * the next value. A non-converted value exits.
561 */
562 do {
563 printf("%08lx:", addr);
Simon Glasscab24b32015-11-26 19:51:29 -0700564#ifdef CONFIG_DM_PCI
565 dm_pci_read_config(dev, addr, &val, size);
566#else
Simon Glass72ef5b62015-11-26 19:51:26 -0700567 val = pci_read_config(bdf, addr, size);
Simon Glasscab24b32015-11-26 19:51:29 -0700568#endif
Simon Glass72ef5b62015-11-26 19:51:26 -0700569 printf(" %0*lx", pci_field_width(size), val);
wdenkc6097192002-11-03 00:24:07 +0000570
Simon Glasse1bf8242014-04-10 20:01:27 -0600571 nbytes = cli_readline(" ? ");
wdenkc6097192002-11-03 00:24:07 +0000572 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
573 /* <CR> pressed as only input, don't modify current
574 * location and move to next. "-" pressed will go back.
575 */
576 if (incrflag)
577 addr += nbytes ? -size : size;
578 nbytes = 1;
Simon Glassb26440f2014-04-10 20:01:31 -0600579 /* good enough to not time out */
580 bootretry_reset_cmd_timeout();
wdenkc6097192002-11-03 00:24:07 +0000581 }
582#ifdef CONFIG_BOOT_RETRY_TIME
583 else if (nbytes == -2) {
584 break; /* timed out, exit the command */
585 }
586#endif
587 else {
588 char *endp;
589 i = simple_strtoul(console_buffer, &endp, 16);
590 nbytes = endp - console_buffer;
591 if (nbytes) {
wdenkc6097192002-11-03 00:24:07 +0000592 /* good enough to not time out
593 */
Simon Glassb26440f2014-04-10 20:01:31 -0600594 bootretry_reset_cmd_timeout();
Simon Glasscab24b32015-11-26 19:51:29 -0700595#ifdef CONFIG_DM_PCI
596 dm_pci_write_config(dev, addr, i, size);
597#else
598 pci_cfg_write(bdf, addr, size, i);
599#endif
wdenkc6097192002-11-03 00:24:07 +0000600 if (incrflag)
601 addr += size;
602 }
603 }
604 } while (nbytes);
605
606 return 0;
607}
608
609/* PCI Configuration Space access commands
610 *
611 * Syntax:
612 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
613 * pci next[.b, .w, .l] bus.device.function [addr]
614 * pci modify[.b, .w, .l] bus.device.function [addr]
615 * pci write[.b, .w, .l] bus.device.function addr value
616 */
Kim Phillips088f1b12012-10-29 13:34:31 +0000617static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenkc6097192002-11-03 00:24:07 +0000618{
Simon Glass72ef5b62015-11-26 19:51:26 -0700619 ulong addr = 0, value = 0, cmd_size = 0;
620 enum pci_size_t size = PCI_SIZE_32;
Simon Glasscab24b32015-11-26 19:51:29 -0700621#ifdef CONFIG_DM_PCI
622 struct udevice *dev, *bus;
623#else
Simon Glass32ec5b32015-11-26 19:51:27 -0700624 pci_dev_t dev;
Simon Glasscab24b32015-11-26 19:51:29 -0700625#endif
Simon Glassca7de762015-11-26 19:51:19 -0700626 int busnum = 0;
wdenkc6097192002-11-03 00:24:07 +0000627 pci_dev_t bdf = 0;
628 char cmd = 's';
Simon Glassbfa41912015-11-26 19:51:18 -0700629 int ret = 0;
wdenkc6097192002-11-03 00:24:07 +0000630
631 if (argc > 1)
632 cmd = argv[1][0];
633
634 switch (cmd) {
635 case 'd': /* display */
636 case 'n': /* next */
637 case 'm': /* modify */
638 case 'w': /* write */
639 /* Check for a size specification. */
Simon Glass72ef5b62015-11-26 19:51:26 -0700640 cmd_size = cmd_get_data_size(argv[1], 4);
641 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
wdenkc6097192002-11-03 00:24:07 +0000642 if (argc > 3)
643 addr = simple_strtoul(argv[3], NULL, 16);
644 if (argc > 4)
645 value = simple_strtoul(argv[4], NULL, 16);
646 case 'h': /* header */
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200647#ifdef CONFIG_DM_PCI
648 case 'b': /* bars */
649#endif
wdenkc6097192002-11-03 00:24:07 +0000650 if (argc < 3)
651 goto usage;
652 if ((bdf = get_pci_dev(argv[2])) == -1)
653 return 1;
654 break;
Stephen Warrene578b922016-01-26 11:10:11 -0700655#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
John Schmoller96d61602010-10-22 00:20:23 -0500656 case 'e':
Stephen Warrene578b922016-01-26 11:10:11 -0700657 pci_init();
658 return 0;
John Schmoller96d61602010-10-22 00:20:23 -0500659#endif
wdenkc6097192002-11-03 00:24:07 +0000660 default: /* scan bus */
661 value = 1; /* short listing */
wdenkc6097192002-11-03 00:24:07 +0000662 if (argc > 1) {
663 if (argv[argc-1][0] == 'l') {
664 value = 0;
665 argc--;
666 }
667 if (argc > 1)
Simon Glassca7de762015-11-26 19:51:19 -0700668 busnum = simple_strtoul(argv[1], NULL, 16);
wdenkc6097192002-11-03 00:24:07 +0000669 }
Simon Glasscab24b32015-11-26 19:51:29 -0700670#ifdef CONFIG_DM_PCI
671 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
672 if (ret) {
673 printf("No such bus\n");
674 return CMD_RET_FAILURE;
675 }
676 pciinfo(bus, value);
677#else
Simon Glassca7de762015-11-26 19:51:19 -0700678 pciinfo(busnum, value);
Simon Glasscab24b32015-11-26 19:51:29 -0700679#endif
wdenkc6097192002-11-03 00:24:07 +0000680 return 0;
681 }
682
Simon Glasscab24b32015-11-26 19:51:29 -0700683#ifdef CONFIG_DM_PCI
Simon Glassf3f1fae2015-11-29 13:17:48 -0700684 ret = dm_pci_bus_find_bdf(bdf, &dev);
Simon Glasscab24b32015-11-26 19:51:29 -0700685 if (ret) {
686 printf("No such device\n");
687 return CMD_RET_FAILURE;
688 }
689#else
Simon Glass32ec5b32015-11-26 19:51:27 -0700690 dev = bdf;
Simon Glasscab24b32015-11-26 19:51:29 -0700691#endif
Simon Glass32ec5b32015-11-26 19:51:27 -0700692
wdenkc6097192002-11-03 00:24:07 +0000693 switch (argv[1][0]) {
694 case 'h': /* header */
Simon Glass32ec5b32015-11-26 19:51:27 -0700695 pci_header_show(dev);
Simon Glassbfa41912015-11-26 19:51:18 -0700696 break;
wdenkc6097192002-11-03 00:24:07 +0000697 case 'd': /* display */
Simon Glass32ec5b32015-11-26 19:51:27 -0700698 return pci_cfg_display(dev, addr, size, value);
wdenkc6097192002-11-03 00:24:07 +0000699 case 'n': /* next */
700 if (argc < 4)
701 goto usage;
Simon Glass32ec5b32015-11-26 19:51:27 -0700702 ret = pci_cfg_modify(dev, addr, size, value, 0);
Simon Glassbfa41912015-11-26 19:51:18 -0700703 break;
wdenkc6097192002-11-03 00:24:07 +0000704 case 'm': /* modify */
705 if (argc < 4)
706 goto usage;
Simon Glass32ec5b32015-11-26 19:51:27 -0700707 ret = pci_cfg_modify(dev, addr, size, value, 1);
Simon Glassbfa41912015-11-26 19:51:18 -0700708 break;
wdenkc6097192002-11-03 00:24:07 +0000709 case 'w': /* write */
710 if (argc < 5)
711 goto usage;
Simon Glasscab24b32015-11-26 19:51:29 -0700712#ifdef CONFIG_DM_PCI
713 ret = dm_pci_write_config(dev, addr, value, size);
714#else
Simon Glass32ec5b32015-11-26 19:51:27 -0700715 ret = pci_cfg_write(dev, addr, size, value);
Simon Glasscab24b32015-11-26 19:51:29 -0700716#endif
Simon Glassbfa41912015-11-26 19:51:18 -0700717 break;
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200718#ifdef CONFIG_DM_PCI
719
720 case 'b': /* bars */
721 return pci_bar_show(dev);
722#endif
Simon Glassbfa41912015-11-26 19:51:18 -0700723 default:
724 ret = CMD_RET_USAGE;
725 break;
wdenkc6097192002-11-03 00:24:07 +0000726 }
727
Simon Glassbfa41912015-11-26 19:51:18 -0700728 return ret;
wdenkc6097192002-11-03 00:24:07 +0000729 usage:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000730 return CMD_RET_USAGE;
wdenkc6097192002-11-03 00:24:07 +0000731}
732
wdenk8bde7f72003-06-27 21:31:46 +0000733/***************************************************/
734
Kim Phillips088f1b12012-10-29 13:34:31 +0000735#ifdef CONFIG_SYS_LONGHELP
736static char pci_help_text[] =
wdenk8bde7f72003-06-27 21:31:46 +0000737 "[bus] [long]\n"
738 " - short or long list of PCI devices on bus 'bus'\n"
Stephen Warrene578b922016-01-26 11:10:11 -0700739#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
John Schmoller96d61602010-10-22 00:20:23 -0500740 "pci enum\n"
Stephen Warrene578b922016-01-26 11:10:11 -0700741 " - Enumerate PCI buses\n"
John Schmoller96d61602010-10-22 00:20:23 -0500742#endif
wdenk8bde7f72003-06-27 21:31:46 +0000743 "pci header b.d.f\n"
744 " - show header of PCI device 'bus.device.function'\n"
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200745#ifdef CONFIG_DM_PCI
746 "pci bar b.d.f\n"
747 " - show BARs base and size for device b.d.f'\n"
748#endif
wdenk8bde7f72003-06-27 21:31:46 +0000749 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
750 " - display PCI configuration space (CFG)\n"
751 "pci next[.b, .w, .l] b.d.f address\n"
752 " - modify, read and keep CFG address\n"
753 "pci modify[.b, .w, .l] b.d.f address\n"
754 " - modify, auto increment CFG address\n"
755 "pci write[.b, .w, .l] b.d.f address value\n"
Kim Phillips088f1b12012-10-29 13:34:31 +0000756 " - write to CFG address";
757#endif
758
759U_BOOT_CMD(
760 pci, 5, 1, do_pci,
761 "list and access PCI Configuration Space", pci_help_text
wdenk8bde7f72003-06-27 21:31:46 +0000762);