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Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
Sascha Lauef14ae412010-08-19 09:38:56 +02002 * (C) Copyright 2007-2010
Stefan Roeseb765ffb2007-06-15 08:18:01 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
Stefan Roesec25dd8f2007-08-23 11:02:37 +020022#include <command.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020023#include <asm/ppc440.h>
Stefan Roese04e6c382007-07-04 10:06:30 +020024#include <asm/processor.h>
Stefan Roese09887762010-09-16 14:30:37 +020025#include <asm/ppc4xx-gpio.h>
Stefan Roese04e6c382007-07-04 10:06:30 +020026#include <asm/io.h>
Sascha Lauef14ae412010-08-19 09:38:56 +020027#include <post.h>
28#include <flash.h>
29#include <mtd/cfi_flash.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020030
31DECLARE_GLOBAL_DATA_PTR;
32
Sascha Lauef14ae412010-08-19 09:38:56 +020033static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
Stefan Roeseb765ffb2007-06-15 08:18:01 +020034
Stefan Roese3ad63872007-08-21 16:27:57 +020035ulong flash_get_size(ulong base, int banknum);
36int misc_init_r_kbd(void);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020037
38int board_early_init_f(void)
39{
40 u32 sdr0_pfc1, sdr0_pfc2;
41 u32 reg;
42
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020043 /* PLB Write pipelining disabled. Denali Core workaround */
Stefan Roese5e7abce2010-09-11 09:31:43 +020044 mtdcr(PLB4A0_ACR, 0xDE000000);
45 mtdcr(PLB4A1_ACR, 0xDE000000);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020046
47 /*--------------------------------------------------------------------
48 * Setup the interrupt controller polarities, triggers, etc.
49 *-------------------------------------------------------------------*/
Stefan Roese952e7762009-09-24 09:55:50 +020050 mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
51 mtdcr(UIC0ER, 0x00000000); /* disable all */
52 mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
53 mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
54 mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
55 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
56 mtdcr(UIC0SR, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020057
Stefan Roese952e7762009-09-24 09:55:50 +020058 mtdcr(UIC1SR, 0xffffffff); /* clear all */
59 mtdcr(UIC1ER, 0x00000000); /* disable all */
60 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
61 mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
62 mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
63 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
64 mtdcr(UIC1SR, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020065
Stefan Roese952e7762009-09-24 09:55:50 +020066 mtdcr(UIC2SR, 0xffffffff); /* clear all */
67 mtdcr(UIC2ER, 0x00000000); /* disable all */
68 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
69 mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
70 mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
71 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
72 mtdcr(UIC2SR, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020073
74 /* Trace Pins are disabled. SDR0_PFC0 Register */
75 mtsdr(SDR0_PFC0, 0x0);
76
77 /* select Ethernet pins */
78 mfsdr(SDR0_PFC1, sdr0_pfc1);
79 /* SMII via ZMII */
80 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
81 SDR0_PFC1_SELECT_CONFIG_6;
82 mfsdr(SDR0_PFC2, sdr0_pfc2);
83 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
84 SDR0_PFC2_SELECT_CONFIG_6;
85
86 /* enable SPI (SCP) */
87 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
88
89 mtsdr(SDR0_PFC2, sdr0_pfc2);
90 mtsdr(SDR0_PFC1, sdr0_pfc1);
91
92 mtsdr(SDR0_PFC4, 0x80000000);
93
94 /* PCI arbiter disabled */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020095 /* PCI Host Configuration disbaled */
Stefan Roesed1c3b272009-09-09 16:25:29 +020096 mfsdr(SDR0_PCI0, reg);
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020097 reg = 0;
Stefan Roesed1c3b272009-09-09 16:25:29 +020098 mtsdr(SDR0_PCI0, 0x00000000 | reg);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
Sascha Lauef14ae412010-08-19 09:38:56 +0200103 /* enable the LSB transmitter */
104 gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
105 /* enable the CAN transmitter */
106 gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100107
108 reg = 0; /* reuse as counter */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
110 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
111 & ~CONFIG_SYS_DSPIC_TEST_MASK);
Sascha Lauef14ae412010-08-19 09:38:56 +0200112 while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100113 udelay(1000);
114 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100116 /* set "boot error" flag */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
118 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
119 CONFIG_SYS_DSPIC_TEST_MASK);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100120 }
121#endif
122
Stefan Roese54fd6c92007-11-13 08:18:20 +0100123 /*
124 * Reset PHY's:
125 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
126 * upon reset, and with the first reset upon powerup, the addresses are
127 * not latched reliable, since the IRQ line is multiplexed with an
128 * MDIO address. A 2nd reset at this time will make sure, that the
129 * correct address is latched.
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
132 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
Stefan Roese54fd6c92007-11-13 08:18:20 +0100133 udelay(1000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
135 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
Stefan Roese54fd6c92007-11-13 08:18:20 +0100136 udelay(1000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
138 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
Stefan Roese54fd6c92007-11-13 08:18:20 +0100139
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200140 return 0;
141}
142
Sascha Lauef14ae412010-08-19 09:38:56 +0200143/*
144 * Override weak default with board specific version
145 */
146phys_addr_t cfi_flash_bank_addr(int bank)
147{
148 return lwmon5_cfi_flash_bank_addr[bank];
149}
150
151/*
152 * Override the weak default mapping function with a board specific one
153 */
154u32 flash_get_bank_size(int cs, int idx)
155{
156 return flash_info[idx].size;
157}
158
159int board_early_init_r(void)
160{
161 u32 val0, val1;
162
163 /*
164 * lwmon5 is manufactured in 2 different board versions:
165 * The lwmon5a board has 64MiB NOR flash instead of the
166 * 128MiB of the original lwmon5. Unfortunately the CFI driver
167 * will report 2 banks of 64MiB even for the smaller flash
168 * chip, since the bank is mirrored. To fix this, we bring
169 * one bank into CFI query mode and read its response. This
170 * enables us to detect the real number of flash devices/
171 * banks which will be used later on by the common CFI driver.
172 */
173
174 /* Put bank 0 into CFI command mode and read */
175 out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
176 val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
177 val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
178
179 /* Reset flash again out of query mode */
180 out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
181
182 /* When not identical, we have 2 different flash devices/banks */
183 if (val0 != val1)
184 return 0;
185
186 /*
187 * Now we're sure that we're running on a LWMON5a board with
188 * only 64MiB NOR flash in one bank:
189 *
190 * Set flash base address and bank count for CFI driver probing.
191 */
192 cfi_flash_num_flash_banks = 1;
193 lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
194
195 return 0;
196}
197
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200198int misc_init_r(void)
199{
200 u32 pbcr;
201 int size_val = 0;
202 u32 reg;
203 unsigned long usb2d0cr = 0;
204 unsigned long usb2phy0cr, usb2h0cr = 0;
Sascha Lauef14ae412010-08-19 09:38:56 +0200205 unsigned long sdr0_pfc1, sdr0_srst;
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200206
207 /*
208 * FLASH stuff...
209 */
210
211 /* Re-do sizing to get full correct info */
212
213 /* adjust flash start and offset */
214 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
215 gd->bd->bi_flashoffset = 0;
216
Stefan Roesed1c3b272009-09-09 16:25:29 +0200217 mfebc(PB0CR, pbcr);
Sascha Lauef14ae412010-08-19 09:38:56 +0200218 size_val = ffs(gd->bd->bi_flashsize) - 21;
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200219 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200220 mtebc(PB0CR, pbcr);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200221
222 /*
223 * Re-check to get correct base address
224 */
225 flash_get_size(gd->bd->bi_flashstart, 0);
226
227 /* Monitor protection ON by default */
Sascha Lauef14ae412010-08-19 09:38:56 +0200228 flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
229 &flash_info[cfi_flash_num_flash_banks - 1]);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200230
231 /* Env protection ON by default */
Sascha Lauef14ae412010-08-19 09:38:56 +0200232 flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
233 CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
234 &flash_info[cfi_flash_num_flash_banks - 1]);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200235
236 /*
237 * USB suff...
238 */
Sascha Lauef14ae412010-08-19 09:38:56 +0200239
240 /* Reset USB */
241 /* Reset of USB2PHY0 must be active at least 10 us */
242 mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
243 udelay(2000);
244
245 mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
246 SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
247 SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
248 udelay(2000);
249
250 /* Errata CHIP_6 */
251
252 /* 1. Set internal PHY configuration */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200253 /* SDR Setting */
254 mfsdr(SDR0_PFC1, sdr0_pfc1);
255 mfsdr(SDR0_USB0, usb2d0cr);
256 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
257 mfsdr(SDR0_USB2H0CR, usb2h0cr);
258
Sascha Lauef14ae412010-08-19 09:38:56 +0200259 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
260 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
261 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
262 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
263 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
264 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
265 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
266 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
267 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
268 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200269
Sascha Lauef14ae412010-08-19 09:38:56 +0200270 /*
271 * An 8-bit/60MHz interface is the only possible alternative
272 * when connecting the Device to the PHY
273 */
274 usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
275 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200276
277 mtsdr(SDR0_PFC1, sdr0_pfc1);
278 mtsdr(SDR0_USB0, usb2d0cr);
279 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
280 mtsdr(SDR0_USB2H0CR, usb2h0cr);
281
Sascha Lauef14ae412010-08-19 09:38:56 +0200282 /* 2. De-assert internal PHY reset */
283 mfsdr(SDR0_SRST1, sdr0_srst);
284 sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
285 mtsdr(SDR0_SRST1, sdr0_srst);
286
287 /* 3. Wait for more than 1 ms */
288 udelay(2000);
289
290 /* 4. De-assert USB 2.0 Host main reset */
291 mfsdr(SDR0_SRST0, sdr0_srst);
292 sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
293 mtsdr(SDR0_SRST0, sdr0_srst);
294 udelay(1000);
295
296 /* 5. De-assert reset of OPB2 cores */
297 mfsdr(SDR0_SRST1, sdr0_srst);
298 sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
299 sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
300 sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
301 mtsdr(SDR0_SRST1, sdr0_srst);
302 udelay(1000);
303
304 /* 6. Set EHCI Configure FLAG */
305
306 /* 7. Reassert internal PHY reset: */
307 mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
308 udelay(1000);
309
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200310 /*
311 * Clear resets
312 */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200313 mtsdr(SDR0_SRST1, 0x00000000);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200314 mtsdr(SDR0_SRST0, 0x00000000);
315
316 printf("USB: Host(int phy) Device(ext phy)\n");
317
318 /*
319 * Clear PLB4A0_ACR[WRP]
320 * This fix will make the MAL burst disabling patch for the Linux
321 * EMAC driver obsolete.
322 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200323 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
324 mtdcr(PLB4A0_ACR, reg);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200325
326 /*
Stefan Roese3ad63872007-08-21 16:27:57 +0200327 * Init matrix keyboard
328 */
329 misc_init_r_kbd();
330
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200331 return 0;
332}
333
334int checkboard(void)
335{
336 char *s = getenv("serial#");
337
Sascha Lauef14ae412010-08-19 09:38:56 +0200338 puts("Board: lwmon5");
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200339
340 if (s != NULL) {
341 puts(", serial# ");
342 puts(s);
343 }
344 putc('\n');
345
346 return (0);
347}
348
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200349void hw_watchdog_reset(void)
350{
351 int val;
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200352#if defined(CONFIG_WD_MAX_RATE)
353 unsigned long long ct = get_ticks();
354
355 /*
356 * Don't allow watch-dog triggering more frequently than
357 * the predefined value CONFIG_WD_MAX_RATE [ticks].
358 */
359 if (ct >= gd->wdt_last) {
360 if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
361 return;
362 } else {
363 /* Time base counter had been reset */
364 if (((unsigned long long)(-1) - gd->wdt_last + ct) <
365 CONFIG_WD_MAX_RATE)
366 return;
367 }
368 gd->wdt_last = get_ticks();
369#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200370
371 /*
372 * Toggle watchdog output
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374 val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
375 gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200376}
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200377
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200378int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200379{
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200380 if (argc < 2)
381 return cmd_usage(cmdtp);
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200382
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200383 if ((strcmp(argv[1], "on") == 0))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200385 else if ((strcmp(argv[1], "off") == 0))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200387 else
388 return cmd_usage(cmdtp);
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200389
390 return 0;
391}
392
393U_BOOT_CMD(
394 eepromwp, 2, 0, do_eeprom_wp,
Peter Tyser2fb26042009-01-27 18:03:12 -0600395 "eeprom write protect off/on",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200396 "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200397);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100398
399#if defined(CONFIG_VIDEO)
400#include <video_fb.h>
401#include <mb862xx.h>
402
403extern GraphicDevice mb862xx;
404
Sascha Lauef14ae412010-08-19 09:38:56 +0200405static const gdc_regs init_regs [] = {
406 { 0x0100, 0x00000f00 },
407 { 0x0020, 0x801401df },
408 { 0x0024, 0x00000000 },
409 { 0x0028, 0x00000000 },
410 { 0x002c, 0x00000000 },
411 { 0x0110, 0x00000000 },
412 { 0x0114, 0x00000000 },
413 { 0x0118, 0x01df0280 },
414 { 0x0004, 0x031f0000 },
415 { 0x0008, 0x027f027f },
416 { 0x000c, 0x015f028f },
417 { 0x0010, 0x020c0000 },
418 { 0x0014, 0x01df01ea },
419 { 0x0018, 0x00000000 },
420 { 0x001c, 0x01e00280 },
421 { 0x0100, 0x80010f00 },
422 { 0x0, 0x0 }
Anatolij Gustschind610a602008-01-11 15:31:09 +0100423};
424
Sascha Lauef14ae412010-08-19 09:38:56 +0200425const gdc_regs *board_get_regs(void)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100426{
427 return init_regs;
428}
429
430/* Returns Lime base address */
Sascha Lauef14ae412010-08-19 09:38:56 +0200431unsigned int board_video_init(void)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100432{
433 /*
434 * Reset Lime controller
435 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100437 udelay(500);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100439
Anatolij Gustschind610a602008-01-11 15:31:09 +0100440 mb862xx.winSizeX = 640;
441 mb862xx.winSizeY = 480;
442 mb862xx.gdfBytesPP = 2;
443 mb862xx.gdfIndex = GDF_15BIT_555RGB;
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445 return CONFIG_SYS_LIME_BASE_0;
Anatolij Gustschind610a602008-01-11 15:31:09 +0100446}
447
Sascha Lauef14ae412010-08-19 09:38:56 +0200448#define DEFAULT_BRIGHTNESS 0x64
Yuri Tikhonov0f855a12008-03-18 13:27:57 +0100449
450static void board_backlight_brightness(int brightness)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100451{
Yuri Tikhonov0f855a12008-03-18 13:27:57 +0100452 if (brightness > 0) {
Anatolij Gustschind610a602008-01-11 15:31:09 +0100453 /* pwm duty, lamp on */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
455 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100456 } else {
457 /* lamp off */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
459 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100460 }
461}
462
Sascha Lauef14ae412010-08-19 09:38:56 +0200463void board_backlight_switch(int flag)
Yuri Tikhonov0f855a12008-03-18 13:27:57 +0100464{
465 char * param;
466 int rc;
467
468 if (flag) {
469 param = getenv("brightness");
470 rc = param ? simple_strtol(param, NULL, 10) : -1;
471 if (rc < 0)
472 rc = DEFAULT_BRIGHTNESS;
473 } else {
474 rc = 0;
475 }
476 board_backlight_brightness(rc);
477}
478
Anatolij Gustschind610a602008-01-11 15:31:09 +0100479#if defined(CONFIG_CONSOLE_EXTRA_INFO)
480/*
481 * Return text to be printed besides the logo.
482 */
Sascha Lauef14ae412010-08-19 09:38:56 +0200483void video_get_info_str(int line_number, char *info)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100484{
Sascha Lauef14ae412010-08-19 09:38:56 +0200485 if (line_number == 1)
486 strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
487 else
Anatolij Gustschind610a602008-01-11 15:31:09 +0100488 info [0] = '\0';
Anatolij Gustschind610a602008-01-11 15:31:09 +0100489}
Sascha Lauef14ae412010-08-19 09:38:56 +0200490#endif /* CONFIG_CONSOLE_EXTRA_INFO */
Anatolij Gustschind610a602008-01-11 15:31:09 +0100491#endif /* CONFIG_VIDEO */
Yuri Tikhonovff818b22008-02-04 17:11:53 +0100492
493void board_reset(void)
494{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495 gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
Yuri Tikhonovff818b22008-02-04 17:11:53 +0100496}