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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
2 * board/mx1ads/syncflash.c
wdenk49822e22004-06-19 21:19:10 +00003 *
wdenk2d24a3a2004-06-09 21:50:45 +00004 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
wdenk281e00a2004-08-01 22:48:16 +000027/*#include <mc9328.h>*/
28#include <asm/arch/imx-regs.h>
wdenk2d24a3a2004-06-09 21:50:45 +000029
30typedef unsigned long * p_u32;
31
32/* 4Mx16x2 IAM=0 CSD1 */
33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
wdenk2d24a3a2004-06-09 21:50:45 +000035
36/* Following Setting is for CSD1 */
wdenk281e00a2004-08-01 22:48:16 +000037#define SFCTL 0x00221004
38#define reg_SFCTL __REG(SFCTL)
wdenk2d24a3a2004-06-09 21:50:45 +000039
wdenk281e00a2004-08-01 22:48:16 +000040#define SYNCFLASH_A10 (0x00100000)
wdenk2d24a3a2004-06-09 21:50:45 +000041
wdenk281e00a2004-08-01 22:48:16 +000042#define CMD_NORMAL (0x81020300) /* Normal Mode */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
44#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
45#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
46#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
wdenk281e00a2004-08-01 22:48:16 +000047#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
wdenk2d24a3a2004-06-09 21:50:45 +000048
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
wdenk2d24a3a2004-06-09 21:50:45 +000050
51/* LCR Command */
wdenk281e00a2004-08-01 22:48:16 +000052#define LCR_READSTATUS (0x0001C000) /* 0x70 */
53#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
54#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
55#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
56#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
wdenk2d24a3a2004-06-09 21:50:45 +000057
Wolfgang Denk53677ef2008-05-20 16:00:29 +020058/* Get Status register */
wdenk2d24a3a2004-06-09 21:50:45 +000059u32 SF_SR(void) {
60 u32 tmp,tmp1;
61
62 reg_SFCTL = CMD_PROGRAM;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 tmp = __REG(CONFIG_SYS_FLASH_BASE);
wdenk49822e22004-06-19 21:19:10 +000064
wdenk2d24a3a2004-06-09 21:50:45 +000065 reg_SFCTL = CMD_NORMAL;
66
Wolfgang Denk53677ef2008-05-20 16:00:29 +020067 reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 tmp1 = __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
wdenk2d24a3a2004-06-09 21:50:45 +000069
70 return tmp;
71}
72
Wolfgang Denk53677ef2008-05-20 16:00:29 +020073/* check if SyncFlash is ready */
wdenk2d24a3a2004-06-09 21:50:45 +000074u8 SF_Ready(void) {
75 u32 tmp;
76
77 tmp = SF_SR();
78
79 if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
80 printf ("SyncFlash Error code %08x\n",tmp);
81 };
82
83 if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
84 printf ("SyncFlash Error code %08x\n",tmp);
wdenk2d24a3a2004-06-09 21:50:45 +000085 };
86
Wolfgang Denk53677ef2008-05-20 16:00:29 +020087 if (tmp == 0x00800080) /* Test Bit 7 of SR */
wdenk2d24a3a2004-06-09 21:50:45 +000088 return 1;
89 else
90 return 0;
91}
92
Wolfgang Denk53677ef2008-05-20 16:00:29 +020093/* Issue the precharge all command */
wdenk2d24a3a2004-06-09 21:50:45 +000094void SF_PrechargeAll(void) {
95
96 u32 tmp;
97
Wolfgang Denk53677ef2008-05-20 16:00:29 +020098 reg_SFCTL = CMD_PREC; /* Set Precharge Command */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 tmp = __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
wdenk2d24a3a2004-06-09 21:50:45 +0000100}
101
102/* set SyncFlash to normal mode */
103void SF_Normal(void) {
104
105 SF_PrechargeAll();
wdenk49822e22004-06-19 21:19:10 +0000106
wdenk2d24a3a2004-06-09 21:50:45 +0000107 reg_SFCTL = CMD_NORMAL;
108}
109
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200110/* Erase SyncFlash */
wdenk2d24a3a2004-06-09 21:50:45 +0000111void SF_Erase(u32 RowAddress) {
112 u32 tmp;
113
114 reg_SFCTL = CMD_NORMAL;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200115 tmp = __REG(RowAddress);
wdenk2d24a3a2004-06-09 21:50:45 +0000116
117 reg_SFCTL = CMD_PREC;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118 tmp = __REG(RowAddress);
wdenk49822e22004-06-19 21:19:10 +0000119
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200120 reg_SFCTL = CMD_LCR; /* Set LCR mode */
121 __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
wdenk49822e22004-06-19 21:19:10 +0000122
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200123 reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
124 __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
wdenk2d24a3a2004-06-09 21:50:45 +0000125
126 while(!SF_Ready());
127}
128
wdenk2d24a3a2004-06-09 21:50:45 +0000129void SF_NvmodeErase(void) {
130 SF_PrechargeAll();
131
132 reg_SFCTL = CMD_LCR; /* Set to LCR mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
wdenk49822e22004-06-19 21:19:10 +0000134
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200135 reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
wdenk2d24a3a2004-06-09 21:50:45 +0000137
138 while(!SF_Ready());
139}
140
141void SF_NvmodeWrite(void) {
142 SF_PrechargeAll();
143
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200144 reg_SFCTL = CMD_LCR; /* Set to LCR mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
wdenk49822e22004-06-19 21:19:10 +0000146
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200147 reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
wdenk2d24a3a2004-06-09 21:50:45 +0000149}
150
wdenk2d24a3a2004-06-09 21:50:45 +0000151/****************************************************************************************/
152
153ulong flash_init(void) {
154 int i, j;
155 u32 tmp;
156
157/* Turn on CSD1 for negating RESETSF of SyncFLash */
158
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200159 reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
wdenk2d24a3a2004-06-09 21:50:45 +0000160 udelay(200);
161
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200162 reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
163 tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
wdenk2d24a3a2004-06-09 21:50:45 +0000164
165 SF_Normal();
wdenk49822e22004-06-19 21:19:10 +0000166
wdenk2d24a3a2004-06-09 21:50:45 +0000167 i = 0;
168
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200169 flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
wdenk49822e22004-06-19 21:19:10 +0000170
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200171 flash_info[i].size = FLASH_BANK_SIZE;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
wdenk2d24a3a2004-06-09 21:50:45 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174 memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
wdenk2d24a3a2004-06-09 21:50:45 +0000175
176 for (j = 0; j < flash_info[i].sector_count; j++) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
wdenk2d24a3a2004-06-09 21:50:45 +0000178 }
wdenk49822e22004-06-19 21:19:10 +0000179
wdenk2d24a3a2004-06-09 21:50:45 +0000180 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 CONFIG_SYS_FLASH_BASE,
182 CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
wdenk2d24a3a2004-06-09 21:50:45 +0000183 &flash_info[0]);
184
185 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200186 CONFIG_ENV_ADDR,
187 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
wdenk2d24a3a2004-06-09 21:50:45 +0000188 &flash_info[0]);
189
190 return FLASH_BANK_SIZE;
191}
192
wdenk2d24a3a2004-06-09 21:50:45 +0000193void flash_print_info (flash_info_t *info) {
194
195 int i;
196
197 switch (info->flash_id & FLASH_VENDMASK) {
198 case (FLASH_MAN_MT & FLASH_VENDMASK):
199 printf("Micron: ");
200 break;
201 default:
202 printf("Unknown Vendor ");
203 break;
204 }
wdenk49822e22004-06-19 21:19:10 +0000205
wdenk2d24a3a2004-06-09 21:50:45 +0000206 switch (info->flash_id & FLASH_TYPEMASK) {
207 case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
208 printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
209 break;
210 default:
211 printf("Unknown Chip Type\n");
212 return;
213 break;
214 }
215
216 printf(" Size: %ld MB in %d Sectors\n",
217 info->size >> 20, info->sector_count);
218
219 printf(" Sector Start Addresses: ");
220
221 for (i = 0; i < info->sector_count; i++) {
wdenk49822e22004-06-19 21:19:10 +0000222 if ((i % 5) == 0)
wdenk2d24a3a2004-06-09 21:50:45 +0000223 printf ("\n ");
224
225 printf (" %08lX%s", info->start[i],
226 info->protect[i] ? " (RO)" : " ");
227 }
wdenk49822e22004-06-19 21:19:10 +0000228
wdenk2d24a3a2004-06-09 21:50:45 +0000229 printf ("\n");
230}
231
wdenk2d24a3a2004-06-09 21:50:45 +0000232/*-----------------------------------------------------------------------*/
233
234int flash_erase (flash_info_t *info, int s_first, int s_last) {
235 int iflag, cflag, prot, sect;
236 int rc = ERR_OK;
237
238/* first look for protection bits */
239
240 if (info->flash_id == FLASH_UNKNOWN)
241 return ERR_UNKNOWN_FLASH_TYPE;
242
wdenk49822e22004-06-19 21:19:10 +0000243 if ((s_first < 0) || (s_first > s_last))
wdenk2d24a3a2004-06-09 21:50:45 +0000244 return ERR_INVAL;
245
wdenk49822e22004-06-19 21:19:10 +0000246 if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
wdenk2d24a3a2004-06-09 21:50:45 +0000247 return ERR_UNKNOWN_FLASH_VENDOR;
248
249 prot = 0;
250
251 for (sect = s_first; sect <= s_last; ++sect) {
wdenk49822e22004-06-19 21:19:10 +0000252 if (info->protect[sect])
wdenk2d24a3a2004-06-09 21:50:45 +0000253 prot++;
254 }
wdenk49822e22004-06-19 21:19:10 +0000255
wdenk2d24a3a2004-06-09 21:50:45 +0000256 if (prot) {
257 printf("protected!\n");
258 return ERR_PROTECTED;
259 }
260/*
261 * Disable interrupts which might cause a timeout
262 * here. Remember that our exception vectors are
263 * at address 0 in the flash, and we don't want a
264 * (ticker) exception to happen while the flash
265 * chip is in programming mode.
266 */
267
268 cflag = icache_status();
269 icache_disable();
270 iflag = disable_interrupts();
271
272/* Start erase on unprotected sectors */
273 for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
wdenk49822e22004-06-19 21:19:10 +0000274
wdenk2d24a3a2004-06-09 21:50:45 +0000275 printf("Erasing sector %2d ... ", sect);
276
277/* arm simple, non interrupt dependent timer */
278
279 reset_timer_masked();
280
281 SF_NvmodeErase();
282 SF_NvmodeWrite();
283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
wdenk2d24a3a2004-06-09 21:50:45 +0000285 SF_Normal();
286
287 printf("ok.\n");
288 }
289
290 if (ctrlc())
291 printf("User Interrupt!\n");
292
293 if (iflag)
294 enable_interrupts();
295
296 if (cflag)
297 icache_enable();
298
299 return rc;
300}
301
wdenk2d24a3a2004-06-09 21:50:45 +0000302/*-----------------------------------------------------------------------
303 * Copy memory to flash.
304 */
305
306int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
307 int i;
308
wdenk49822e22004-06-19 21:19:10 +0000309 for(i = 0; i < cnt; i += 4) {
wdenk2d24a3a2004-06-09 21:50:45 +0000310
311 SF_PrechargeAll();
312
313 reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
314 __REG(addr + i) = __REG((u32)src + i);
315
316 while(!SF_Ready());
317 }
318
319 SF_Normal();
wdenk49822e22004-06-19 21:19:10 +0000320
wdenk2d24a3a2004-06-09 21:50:45 +0000321 return ERR_OK;
322}