| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
| 4 | * Scott McNutt <smcnutt@psyent.com> |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_NIOS2_CACHE_H_ |
| 8 | #define __ASM_NIOS2_CACHE_H_ |
| 9 | |
| Anton Staaf | 6fa6035 | 2011-10-17 16:46:05 -0700 | [diff] [blame] | 10 | /* |
| Thomas Chou | 21ff734 | 2015-10-23 07:58:20 +0800 | [diff] [blame] | 11 | * Valid L1 data cache line sizes for the NIOS2 architecture are 4, |
| 12 | * 16, and 32 bytes. We default to the largest of these values for |
| 13 | * alignment of DMA buffers. |
| Anton Staaf | 6fa6035 | 2011-10-17 16:46:05 -0700 | [diff] [blame] | 14 | */ |
| Anton Staaf | 6fa6035 | 2011-10-17 16:46:05 -0700 | [diff] [blame] | 15 | #define ARCH_DMA_MINALIGN 32 |
| Anton Staaf | 6fa6035 | 2011-10-17 16:46:05 -0700 | [diff] [blame] | 16 | |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 17 | #endif /* __ASM_NIOS2_CACHE_H_ */ |