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Sergey Kubushync74b2102007-08-10 20:26:18 +02001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
4 * Based on:
5 *
6 * ----------------------------------------------------------------------------
7 *
8 * dm644x_emac.h
9 *
10 * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
11 *
12 * Copyright (C) 2005 Texas Instruments.
13 *
14 * ----------------------------------------------------------------------------
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * ----------------------------------------------------------------------------
30
31 * Modifications:
32 * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
33 *
34 */
35
36#ifndef _DM644X_EMAC_H_
37#define _DM644X_EMAC_H_
38
39#include <asm/arch/hardware.h>
40
41#define EMAC_BASE_ADDR (0x01c80000)
42#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
43#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
44#define EMAC_MDIO_BASE_ADDR (0x01c84000)
45
46/* MDIO module input frequency */
47#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
48/* MDIO clock output frequency */
49#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
50
51/* Ethernet Min/Max packet size */
52#define EMAC_MIN_ETHERNET_PKT_SIZE 60
53#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
54#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
55
56/* Number of RX packet buffers
57 * NOTE: Only 1 buffer supported as of now
58 */
59#define EMAC_MAX_RX_BUFFERS 10
60
61
62/***********************************************
63 ******** Internally used macros ***************
64 ***********************************************/
65
66#define EMAC_CH_TX 1
67#define EMAC_CH_RX 0
68
69/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
70 * reserve space for 64 descriptors max
71 */
72#define EMAC_RX_DESC_BASE 0x0
73#define EMAC_TX_DESC_BASE 0x1000
74
75/* EMAC Teardown value */
76#define EMAC_TEARDOWN_VALUE 0xfffffffc
77
78/* MII Status Register */
79#define MII_STATUS_REG 1
80
81/* Number of statistics registers */
82#define EMAC_NUM_STATS 36
83
84
85/* EMAC Descriptor */
86typedef volatile struct _emac_desc
87{
88 u_int32_t next; /* Pointer to next descriptor in chain */
89 u_int8_t *buffer; /* Pointer to data buffer */
90 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
91 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
92} emac_desc;
93
94/* CPPI bit positions */
95#define EMAC_CPPI_SOP_BIT (0x80000000)
96#define EMAC_CPPI_EOP_BIT (0x40000000)
97#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
98#define EMAC_CPPI_EOQ_BIT (0x10000000)
99#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
100#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
101
102#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
103
104#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
105#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
106
107#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
108#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
109
110
111#define MDIO_CONTROL_IDLE (0x80000000)
112#define MDIO_CONTROL_ENABLE (0x40000000)
113#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
114#define MDIO_CONTROL_FAULT (0x80000)
115#define MDIO_USERACCESS0_GO (0x80000000)
116#define MDIO_USERACCESS0_WRITE_READ (0x0)
117#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
118#define MDIO_USERACCESS0_ACK (0x20000000)
119
120/* Ethernet MAC Registers Structure */
121typedef struct {
122 dv_reg TXIDVER;
123 dv_reg TXCONTROL;
124 dv_reg TXTEARDOWN;
125 u_int8_t RSVD0[4];
126 dv_reg RXIDVER;
127 dv_reg RXCONTROL;
128 dv_reg RXTEARDOWN;
129 u_int8_t RSVD1[100];
130 dv_reg TXINTSTATRAW;
131 dv_reg TXINTSTATMASKED;
132 dv_reg TXINTMASKSET;
133 dv_reg TXINTMASKCLEAR;
134 dv_reg MACINVECTOR;
135 u_int8_t RSVD2[12];
136 dv_reg RXINTSTATRAW;
137 dv_reg RXINTSTATMASKED;
138 dv_reg RXINTMASKSET;
139 dv_reg RXINTMASKCLEAR;
140 dv_reg MACINTSTATRAW;
141 dv_reg MACINTSTATMASKED;
142 dv_reg MACINTMASKSET;
143 dv_reg MACINTMASKCLEAR;
144 u_int8_t RSVD3[64];
145 dv_reg RXMBPENABLE;
146 dv_reg RXUNICASTSET;
147 dv_reg RXUNICASTCLEAR;
148 dv_reg RXMAXLEN;
149 dv_reg RXBUFFEROFFSET;
150 dv_reg RXFILTERLOWTHRESH;
151 u_int8_t RSVD4[8];
152 dv_reg RX0FLOWTHRESH;
153 dv_reg RX1FLOWTHRESH;
154 dv_reg RX2FLOWTHRESH;
155 dv_reg RX3FLOWTHRESH;
156 dv_reg RX4FLOWTHRESH;
157 dv_reg RX5FLOWTHRESH;
158 dv_reg RX6FLOWTHRESH;
159 dv_reg RX7FLOWTHRESH;
160 dv_reg RX0FREEBUFFER;
161 dv_reg RX1FREEBUFFER;
162 dv_reg RX2FREEBUFFER;
163 dv_reg RX3FREEBUFFER;
164 dv_reg RX4FREEBUFFER;
165 dv_reg RX5FREEBUFFER;
166 dv_reg RX6FREEBUFFER;
167 dv_reg RX7FREEBUFFER;
168 dv_reg MACCONTROL;
169 dv_reg MACSTATUS;
170 dv_reg EMCONTROL;
171 dv_reg FIFOCONTROL;
172 dv_reg MACCONFIG;
173 dv_reg SOFTRESET;
174 u_int8_t RSVD5[88];
175 dv_reg MACSRCADDRLO;
176 dv_reg MACSRCADDRHI;
177 dv_reg MACHASH1;
178 dv_reg MACHASH2;
179 dv_reg BOFFTEST;
180 dv_reg TPACETEST;
181 dv_reg RXPAUSE;
182 dv_reg TXPAUSE;
183 u_int8_t RSVD6[16];
184 dv_reg RXGOODFRAMES;
185 dv_reg RXBCASTFRAMES;
186 dv_reg RXMCASTFRAMES;
187 dv_reg RXPAUSEFRAMES;
188 dv_reg RXCRCERRORS;
189 dv_reg RXALIGNCODEERRORS;
190 dv_reg RXOVERSIZED;
191 dv_reg RXJABBER;
192 dv_reg RXUNDERSIZED;
193 dv_reg RXFRAGMENTS;
194 dv_reg RXFILTERED;
195 dv_reg RXQOSFILTERED;
196 dv_reg RXOCTETS;
197 dv_reg TXGOODFRAMES;
198 dv_reg TXBCASTFRAMES;
199 dv_reg TXMCASTFRAMES;
200 dv_reg TXPAUSEFRAMES;
201 dv_reg TXDEFERRED;
202 dv_reg TXCOLLISION;
203 dv_reg TXSINGLECOLL;
204 dv_reg TXMULTICOLL;
205 dv_reg TXEXCESSIVECOLL;
206 dv_reg TXLATECOLL;
207 dv_reg TXUNDERRUN;
208 dv_reg TXCARRIERSENSE;
209 dv_reg TXOCTETS;
210 dv_reg FRAME64;
211 dv_reg FRAME65T127;
212 dv_reg FRAME128T255;
213 dv_reg FRAME256T511;
214 dv_reg FRAME512T1023;
215 dv_reg FRAME1024TUP;
216 dv_reg NETOCTETS;
217 dv_reg RXSOFOVERRUNS;
218 dv_reg RXMOFOVERRUNS;
219 dv_reg RXDMAOVERRUNS;
220 u_int8_t RSVD7[624];
221 dv_reg MACADDRLO;
222 dv_reg MACADDRHI;
223 dv_reg MACINDEX;
224 u_int8_t RSVD8[244];
225 dv_reg TX0HDP;
226 dv_reg TX1HDP;
227 dv_reg TX2HDP;
228 dv_reg TX3HDP;
229 dv_reg TX4HDP;
230 dv_reg TX5HDP;
231 dv_reg TX6HDP;
232 dv_reg TX7HDP;
233 dv_reg RX0HDP;
234 dv_reg RX1HDP;
235 dv_reg RX2HDP;
236 dv_reg RX3HDP;
237 dv_reg RX4HDP;
238 dv_reg RX5HDP;
239 dv_reg RX6HDP;
240 dv_reg RX7HDP;
241 dv_reg TX0CP;
242 dv_reg TX1CP;
243 dv_reg TX2CP;
244 dv_reg TX3CP;
245 dv_reg TX4CP;
246 dv_reg TX5CP;
247 dv_reg TX6CP;
248 dv_reg TX7CP;
249 dv_reg RX0CP;
250 dv_reg RX1CP;
251 dv_reg RX2CP;
252 dv_reg RX3CP;
253 dv_reg RX4CP;
254 dv_reg RX5CP;
255 dv_reg RX6CP;
256 dv_reg RX7CP;
257} emac_regs;
258
259/* EMAC Wrapper Registers Structure */
260typedef struct {
261 u_int8_t RSVD0[4100];
262 dv_reg EWCTL;
263 dv_reg EWINTTCNT;
264} ewrap_regs;
265
266
267/* EMAC MDIO Registers Structure */
268typedef struct {
269 dv_reg VERSION;
270 dv_reg CONTROL;
271 dv_reg ALIVE;
272 dv_reg LINK;
273 dv_reg LINKINTRAW;
274 dv_reg LINKINTMASKED;
275 u_int8_t RSVD0[8];
276 dv_reg USERINTRAW;
277 dv_reg USERINTMASKED;
278 dv_reg USERINTMASKSET;
279 dv_reg USERINTMASKCLEAR;
280 u_int8_t RSVD1[80];
281 dv_reg USERACCESS0;
282 dv_reg USERPHYSEL0;
283 dv_reg USERACCESS1;
284 dv_reg USERPHYSEL1;
285} mdio_regs;
286
Jean-Christophe PLAGNIOL-VILLARDd6e04252008-08-31 04:45:42 +0200287int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
288int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200289
290typedef struct
291{
292 char name[64];
293 int (*init)(int phy_addr);
294 int (*is_phy_connected)(int phy_addr);
295 int (*get_link_speed)(int phy_addr);
296 int (*auto_negotiate)(int phy_addr);
297} phy_t;
298
299#define PHY_LXT972 (0x001378e2)
300int lxt972_is_phy_connected(int phy_addr);
301int lxt972_get_link_speed(int phy_addr);
302int lxt972_init_phy(int phy_addr);
303int lxt972_auto_negotiate(int phy_addr);
304
305#define PHY_DP83848 (0x20005c90)
306int dp83848_is_phy_connected(int phy_addr);
307int dp83848_get_link_speed(int phy_addr);
308int dp83848_init_phy(int phy_addr);
309int dp83848_auto_negotiate(int phy_addr);
310
311#endif /* _DM644X_EMAC_H_ */