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Vladimir Barinov60c04672015-02-14 01:06:13 +03001/*
2 * include/configs/porter.h
3 * This file is Porter board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __PORTER_H
12#define __PORTER_H
13
14#undef DEBUG
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090015#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
Vladimir Barinov60c04672015-02-14 01:06:13 +030016
17#include "rcar-gen2-common.h"
18
Marek Vasut7ee37d02018-02-16 01:33:27 +010019#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
20#define STACK_AREA_SIZE 0x00100000
Vladimir Barinov60c04672015-02-14 01:06:13 +030021#define LOW_LEVEL_MERAM_STACK \
22 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
23
24/* MEMORY */
25#define RCAR_GEN2_SDRAM_BASE 0x40000000
26#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
27#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
28
29/* SCIF */
Vladimir Barinov60c04672015-02-14 01:06:13 +030030
31/* FLASH */
32#define CONFIG_SPI
Vladimir Barinov60c04672015-02-14 01:06:13 +030033#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinov60c04672015-02-14 01:06:13 +030034
35/* SH Ether */
Vladimir Barinov60c04672015-02-14 01:06:13 +030036#define CONFIG_SH_ETHER_USE_PORT 0
37#define CONFIG_SH_ETHER_PHY_ADDR 0x1
38#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
39#define CONFIG_SH_ETHER_CACHE_WRITEBACK
40#define CONFIG_SH_ETHER_CACHE_INVALIDATE
41#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinov60c04672015-02-14 01:06:13 +030042#define CONFIG_BITBANGMII
43#define CONFIG_BITBANGMII_MULTI
44
45/* Board Clock */
46#define RMOBILE_XTAL_CLK 20000000u
47#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
48#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Vladimir Barinov60c04672015-02-14 01:06:13 +030049
50#define CONFIG_SYS_TMU_CLK_DIV 4
51
52/* i2c */
Vladimir Barinov60c04672015-02-14 01:06:13 +030053#define CONFIG_SYS_I2C
54#define CONFIG_SYS_I2C_SH
55#define CONFIG_SYS_I2C_SLAVE 0x7F
56#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
57#define CONFIG_SYS_I2C_SH_SPEED0 400000
58#define CONFIG_SYS_I2C_SH_SPEED1 400000
59#define CONFIG_SYS_I2C_SH_SPEED2 400000
60#define CONFIG_SH_I2C_DATA_HIGH 4
61#define CONFIG_SH_I2C_DATA_LOW 5
62#define CONFIG_SH_I2C_CLOCK 10000000
63
64#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
65
Marek Vasut7b8eeb42018-02-17 01:21:15 +010066#define CONFIG_EXTRA_ENV_SETTINGS \
67 "fdt_high=0xffffffff\0" \
68 "initrd_high=0xffffffff\0"
69
Marek Vasut7ee37d02018-02-16 01:33:27 +010070/* SPL support */
71#define CONFIG_SPL_TEXT_BASE 0xe6304000
72#define CONFIG_SPL_STACK 0xe6340000
73#define CONFIG_SPL_MAX_SIZE 0x40000
74#define CONFIG_SPL_SPI_LOAD
75#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
76
Vladimir Barinov60c04672015-02-14 01:06:13 +030077#endif /* __PORTER_H */