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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------
2 . smc91111.h - macros for the LAN91C111 Ethernet Driver
3 .
4 . (C) Copyright 2002
5 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 . Rolf Offermanns <rof@sysgo.de>
7 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
8 . Developed by Simple Network Magic Corporation (SNMC)
9 . Copyright (C) 1996 by Erik Stahlman (ES)
10 .
11 . This program is free software; you can redistribute it and/or modify
12 . it under the terms of the GNU General Public License as published by
13 . the Free Software Foundation; either version 2 of the License, or
14 . (at your option) any later version.
15 .
16 . This program is distributed in the hope that it will be useful,
17 . but WITHOUT ANY WARRANTY; without even the implied warranty of
18 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 . GNU General Public License for more details.
20 .
21 . You should have received a copy of the GNU General Public License
22 . along with this program; if not, write to the Free Software
23 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 .
25 . This file contains register information and access macros for
26 . the LAN91C111 single chip ethernet controller. It is a modified
27 . version of the smc9194.h file.
28 .
29 . Information contained in this file was obtained from the LAN91C111
30 . manual from SMC. To get a copy, if you really want one, you can find
31 . information under www.smsc.com.
32 .
33 . Authors
34 . Erik Stahlman ( erik@vt.edu )
35 . Daris A Nevil ( dnevil@snmc.com )
36 .
37 . History
38 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
39 .
40 ---------------------------------------------------------------------------*/
41#ifndef _SMC91111_H_
42#define _SMC91111_H_
43
44#include <asm/types.h>
45#include <config.h>
46
47/*
48 * This function may be called by the board specific initialisation code
49 * in order to override the default mac address.
50 */
51
52void smc_set_mac_addr(const char *addr);
53
54
55/* I want some simple types */
56
57typedef unsigned char byte;
58typedef unsigned short word;
59typedef unsigned long int dword;
60
61/*
62 . DEBUGGING LEVELS
63 .
64 . 0 for normal operation
65 . 1 for slightly more details
66 . >2 for various levels of increasingly useless information
67 . 2 for interrupt tracking, status flags
68 . 3 for packet info
69 . 4 for complete packet dumps
70*/
71/*#define SMC_DEBUG 0 */
72
73/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
74
75#define SMC_IO_EXTENT 16
76
77#ifdef CONFIG_PXA250
78
wdenkca0e7742004-06-09 15:37:23 +000079#ifdef CONFIG_XSENGINE
80#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
81#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
82#define SMC_inb(p) ({ \
83 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
84 unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
85 if (__p & 2) __v >>= 8; \
86 else __v &= 0xff; \
87 __v; })
wdenk1f6d4252004-11-02 13:00:33 +000088#elif defined(CONFIG_XAENIAX)
89#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
90#define SMC_inw(z) ({ \
91 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \
92 unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
93 if (__p & 3) __v >>= 16; \
94 else __v &= 0xffff; \
95 __v; })
96#define SMC_inb(p) ({ \
97 unsigned int ___v = SMC_inw((p) & ~1); \
98 if (p & 1) ___v >>= 8; \
99 else ___v &= 0xff; \
100 ___v; })
wdenkca0e7742004-06-09 15:37:23 +0000101#else
wdenkfe8c2802002-11-03 00:38:21 +0000102#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
103#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
104#define SMC_inb(p) ({ \
105 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
wdenk487778b2003-06-06 11:20:01 +0000106 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
wdenkfe8c2802002-11-03 00:38:21 +0000107 if (__p & 1) __v >>= 8; \
108 else __v &= 0xff; \
109 __v; })
wdenkca0e7742004-06-09 15:37:23 +0000110#endif
wdenkfe8c2802002-11-03 00:38:21 +0000111
wdenkca0e7742004-06-09 15:37:23 +0000112#ifdef CONFIG_XSENGINE
113#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
114#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d)
wdenk1f6d4252004-11-02 13:00:33 +0000115#elif defined (CONFIG_XAENIAX)
116#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
117#define SMC_outw(d,p) ({ \
118 dword __dwo = SMC_inl((p) & ~3); \
119 dword __dwn = (word)(d); \
120 __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
121 __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
122 SMC_outl(__dwo, (p) & ~3); \
123})
wdenkca0e7742004-06-09 15:37:23 +0000124#else
wdenkfe8c2802002-11-03 00:38:21 +0000125#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
126#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
wdenkca0e7742004-06-09 15:37:23 +0000127#endif
128
wdenkfe8c2802002-11-03 00:38:21 +0000129#define SMC_outb(d,r) ({ word __d = (byte)(d); \
130 word __w = SMC_inw((r)&~1); \
131 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
132 __w |= ((r)&1) ? __d<<8 : __d; \
133 SMC_outw(__w,(r)&~1); \
134 })
135
136#define SMC_outsl(r,b,l) ({ int __i; \
137 dword *__b2; \
138 __b2 = (dword *) b; \
139 for (__i = 0; __i < l; __i++) { \
140 SMC_outl( *(__b2 + __i), r); \
141 } \
142 })
143
144#define SMC_outsw(r,b,l) ({ int __i; \
145 word *__b2; \
146 __b2 = (word *) b; \
147 for (__i = 0; __i < l; __i++) { \
148 SMC_outw( *(__b2 + __i), r); \
149 } \
150 })
151
152#define SMC_insl(r,b,l) ({ int __i ; \
153 dword *__b2; \
154 __b2 = (dword *) b; \
155 for (__i = 0; __i < l; __i++) { \
156 *(__b2 + __i) = SMC_inl(r); \
157 SMC_inl(0); \
158 }; \
159 })
160
161#define SMC_insw(r,b,l) ({ int __i ; \
162 word *__b2; \
163 __b2 = (word *) b; \
164 for (__i = 0; __i < l; __i++) { \
165 *(__b2 + __i) = SMC_inw(r); \
166 SMC_inw(0); \
167 }; \
168 })
169
170#define SMC_insb(r,b,l) ({ int __i ; \
171 byte *__b2; \
172 __b2 = (byte *) b; \
173 for (__i = 0; __i < l; __i++) { \
174 *(__b2 + __i) = SMC_inb(r); \
175 SMC_inb(0); \
176 }; \
177 })
178
179#else /* if not CONFIG_PXA250 */
180
wdenkc3c7f862004-06-09 14:47:54 +0000181#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
wdenkfe8c2802002-11-03 00:38:21 +0000182/*
183 * We have only 16 Bit PCMCIA access on Socket 0
184 */
185
wdenkaaf224a2004-03-14 15:20:55 +0000186#ifdef CONFIG_ADNPESC1
187#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
188#else
wdenkfe8c2802002-11-03 00:38:21 +0000189#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
wdenkaaf224a2004-03-14 15:20:55 +0000190#endif
wdenkfe8c2802002-11-03 00:38:21 +0000191#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
192
wdenkaaf224a2004-03-14 15:20:55 +0000193#ifdef CONFIG_ADNPESC1
194#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
195#else
wdenkfe8c2802002-11-03 00:38:21 +0000196#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
wdenkaaf224a2004-03-14 15:20:55 +0000197#endif
wdenkfe8c2802002-11-03 00:38:21 +0000198#define SMC_outb(d,r) ({ word __d = (byte)(d); \
199 word __w = SMC_inw((r)&~1); \
200 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
201 __w |= ((r)&1) ? __d<<8 : __d; \
202 SMC_outw(__w,(r)&~1); \
203 })
204#if 0
205#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
206#else
207#define SMC_outsw(r,b,l) ({ int __i; \
208 word *__b2; \
209 __b2 = (word *) b; \
210 for (__i = 0; __i < l; __i++) { \
211 SMC_outw( *(__b2 + __i), r); \
212 } \
213 })
214#endif
215
216#if 0
217#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
218#else
219#define SMC_insw(r,b,l) ({ int __i ; \
220 word *__b2; \
221 __b2 = (word *) b; \
222 for (__i = 0; __i < l; __i++) { \
223 *(__b2 + __i) = SMC_inw(r); \
224 SMC_inw(0); \
225 }; \
226 })
227#endif
228
wdenkc3c7f862004-06-09 14:47:54 +0000229#endif /* CONFIG_SMC_USE_IOFUNCS */
230
wdenka3ad8e22003-10-19 23:22:11 +0000231#if defined(CONFIG_SMC_USE_32_BIT)
232
wdenkca0e7742004-06-09 15:37:23 +0000233#ifdef CONFIG_XSENGINE
234#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
235#else
wdenka3ad8e22003-10-19 23:22:11 +0000236#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
wdenkca0e7742004-06-09 15:37:23 +0000237#endif
wdenka3ad8e22003-10-19 23:22:11 +0000238
239#define SMC_insl(r,b,l) ({ int __i ; \
240 dword *__b2; \
241 __b2 = (dword *) b; \
242 for (__i = 0; __i < l; __i++) { \
243 *(__b2 + __i) = SMC_inl(r); \
244 SMC_inl(0); \
245 }; \
246 })
247
wdenkca0e7742004-06-09 15:37:23 +0000248#ifdef CONFIG_XSENGINE
249#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
250#else
wdenka3ad8e22003-10-19 23:22:11 +0000251#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
wdenkca0e7742004-06-09 15:37:23 +0000252#endif
wdenka3ad8e22003-10-19 23:22:11 +0000253#define SMC_outsl(r,b,l) ({ int __i; \
254 dword *__b2; \
255 __b2 = (dword *) b; \
256 for (__i = 0; __i < l; __i++) { \
257 SMC_outl( *(__b2 + __i), r); \
258 } \
259 })
260
261#endif /* CONFIG_SMC_USE_32_BIT */
262
wdenkfe8c2802002-11-03 00:38:21 +0000263#endif
264
265/*---------------------------------------------------------------
266 .
267 . A description of the SMSC registers is probably in order here,
268 . although for details, the SMC datasheet is invaluable.
269 .
270 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
271 . are accessed by writing a number into the BANK_SELECT register
272 . ( I also use a SMC_SELECT_BANK macro for this ).
273 .
274 . The banks are configured so that for most purposes, bank 2 is all
275 . that is needed for simple run time tasks.
276 -----------------------------------------------------------------------*/
277
278/*
279 . Bank Select Register:
280 .
281 . yyyy yyyy 0000 00xx
282 . xx = bank number
283 . yyyy yyyy = 0x33, for identification purposes.
284*/
285#define BANK_SELECT 14
286
287/* Transmit Control Register */
288/* BANK 0 */
289#define TCR_REG 0x0000 /* transmit control register */
290#define TCR_ENABLE 0x0001 /* When 1 we can transmit */
291#define TCR_LOOP 0x0002 /* Controls output pin LBK */
292#define TCR_FORCOL 0x0004 /* When 1 will force a collision */
293#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
294#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
295#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
296#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
297#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
298#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
299#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
300
301#define TCR_CLEAR 0 /* do NOTHING */
302/* the default settings for the TCR register : */
303/* QUESTION: do I want to enable padding of short packets ? */
304#define TCR_DEFAULT TCR_ENABLE
305
306
307/* EPH Status Register */
308/* BANK 0 */
309#define EPH_STATUS_REG 0x0002
310#define ES_TX_SUC 0x0001 /* Last TX was successful */
311#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
312#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
313#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
314#define ES_16COL 0x0010 /* 16 Collisions Reached */
315#define ES_SQET 0x0020 /* Signal Quality Error Test */
316#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
317#define ES_TXDEFR 0x0080 /* Transmit Deferred */
318#define ES_LATCOL 0x0200 /* Late collision detected on last tx */
319#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
320#define ES_EXC_DEF 0x0800 /* Excessive Deferral */
321#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
322#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
323#define ES_TXUNRN 0x8000 /* Tx Underrun */
324
325
326/* Receive Control Register */
327/* BANK 0 */
328#define RCR_REG 0x0004
329#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
330#define RCR_PRMS 0x0002 /* Enable promiscuous mode */
331#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
332#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
333#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
334#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
335#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
336#define RCR_SOFTRST 0x8000 /* resets the chip */
337
338/* the normal settings for the RCR register : */
339#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
340#define RCR_CLEAR 0x0 /* set it to a base state */
341
342/* Counter Register */
343/* BANK 0 */
344#define COUNTER_REG 0x0006
345
346/* Memory Information Register */
347/* BANK 0 */
348#define MIR_REG 0x0008
349
350/* Receive/Phy Control Register */
351/* BANK 0 */
352#define RPC_REG 0x000A
353#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
354#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
355#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
356#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
357#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
358#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
359#define RPC_LED_RES (0x01) /* LED = Reserved */
360#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
361#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
362#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
363#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
364#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
365#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
wdenkc935d3b2004-01-03 19:43:48 +0000366#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
wdenk8bf3b002003-12-06 23:20:41 +0000367/* buggy schematic: LEDa -> yellow, LEDb --> green */
368#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
369 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
370 | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
wdenkaaf224a2004-03-14 15:20:55 +0000371#elif defined(CONFIG_ADNPESC1)
372/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
373#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
374 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
375 | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
wdenk8bf3b002003-12-06 23:20:41 +0000376#else
377/* SMSC reference design: LEDa --> green, LEDb --> yellow */
378#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
379 | (RPC_LED_100_10 << RPC_LSXA_SHFT) \
380 | (RPC_LED_TX_RX << RPC_LSXB_SHFT) )
381#endif
wdenkfe8c2802002-11-03 00:38:21 +0000382
383/* Bank 0 0x000C is reserved */
384
385/* Bank Select Register */
386/* All Banks */
387#define BSR_REG 0x000E
388
389
390/* Configuration Reg */
391/* BANK 1 */
392#define CONFIG_REG 0x0000
393#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
394#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
395#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
396#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
397
398/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
399#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
400
401
402/* Base Address Register */
403/* BANK 1 */
404#define BASE_REG 0x0002
405
406
407/* Individual Address Registers */
408/* BANK 1 */
409#define ADDR0_REG 0x0004
410#define ADDR1_REG 0x0006
411#define ADDR2_REG 0x0008
412
413
414/* General Purpose Register */
415/* BANK 1 */
416#define GP_REG 0x000A
417
418
419/* Control Register */
420/* BANK 1 */
421#define CTL_REG 0x000C
422#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
423#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
424#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
425#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
426#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
427#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
428#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
429#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
wdenk518e2e12004-03-25 14:59:05 +0000430#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/
wdenkfe8c2802002-11-03 00:38:21 +0000431
432/* MMU Command Register */
433/* BANK 2 */
434#define MMU_CMD_REG 0x0000
435#define MC_BUSY 1 /* When 1 the last release has not completed */
436#define MC_NOP (0<<5) /* No Op */
437#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
438#define MC_RESET (2<<5) /* Reset MMU to initial state */
439#define MC_REMOVE (3<<5) /* Remove the current rx packet */
440#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
441#define MC_FREEPKT (5<<5) /* Release packet in PNR register */
442#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
443#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
444
445
446/* Packet Number Register */
447/* BANK 2 */
448#define PN_REG 0x0002
449
450
451/* Allocation Result Register */
452/* BANK 2 */
453#define AR_REG 0x0003
454#define AR_FAILED 0x80 /* Alocation Failed */
455
456
457/* RX FIFO Ports Register */
458/* BANK 2 */
459#define RXFIFO_REG 0x0004 /* Must be read as a word */
460#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
461
462
463/* TX FIFO Ports Register */
464/* BANK 2 */
465#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
466#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
467
468
469/* Pointer Register */
470/* BANK 2 */
471#define PTR_REG 0x0006
472#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
473#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
474#define PTR_READ 0x2000 /* When 1 the operation is a read */
wdenk518e2e12004-03-25 14:59:05 +0000475#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
wdenkfe8c2802002-11-03 00:38:21 +0000476
477
478/* Data Register */
479/* BANK 2 */
480#define SMC91111_DATA_REG 0x0008
481
482
483/* Interrupt Status/Acknowledge Register */
484/* BANK 2 */
485#define SMC91111_INT_REG 0x000C
486
487
488/* Interrupt Mask Register */
489/* BANK 2 */
490#define IM_REG 0x000D
491#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
492#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
493#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
494#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
495#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
496#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
497#define IM_TX_INT 0x02 /* Transmit Interrrupt */
498#define IM_RCV_INT 0x01 /* Receive Interrupt */
499
500
501/* Multicast Table Registers */
502/* BANK 3 */
503#define MCAST_REG1 0x0000
504#define MCAST_REG2 0x0002
505#define MCAST_REG3 0x0004
506#define MCAST_REG4 0x0006
507
508
509/* Management Interface Register (MII) */
510/* BANK 3 */
511#define MII_REG 0x0008
512#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
513#define MII_MDOE 0x0008 /* MII Output Enable */
514#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
515#define MII_MDI 0x0002 /* MII Input, pin MDI */
516#define MII_MDO 0x0001 /* MII Output, pin MDO */
517
518
519/* Revision Register */
520/* BANK 3 */
521#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
522
523
524/* Early RCV Register */
525/* BANK 3 */
526/* this is NOT on SMC9192 */
527#define ERCV_REG 0x000C
528#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
529#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
530
531/* External Register */
532/* BANK 7 */
533#define EXT_REG 0x0000
534
535
536#define CHIP_9192 3
537#define CHIP_9194 4
538#define CHIP_9195 5
539#define CHIP_9196 6
540#define CHIP_91100 7
541#define CHIP_91100FD 8
542#define CHIP_91111FD 9
543
544#if 0
545static const char * chip_ids[ 15 ] = {
546 NULL, NULL, NULL,
547 /* 3 */ "SMC91C90/91C92",
548 /* 4 */ "SMC91C94",
549 /* 5 */ "SMC91C95",
550 /* 6 */ "SMC91C96",
551 /* 7 */ "SMC91C100",
552 /* 8 */ "SMC91C100FD",
553 /* 9 */ "SMC91C111",
554 NULL, NULL,
555 NULL, NULL, NULL};
556#endif
557
558/*
559 . Transmit status bits
560*/
561#define TS_SUCCESS 0x0001
562#define TS_LOSTCAR 0x0400
563#define TS_LATCOL 0x0200
564#define TS_16COL 0x0010
565
566/*
567 . Receive status bits
568*/
569#define RS_ALGNERR 0x8000
570#define RS_BRODCAST 0x4000
571#define RS_BADCRC 0x2000
572#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
573#define RS_TOOLONG 0x0800
574#define RS_TOOSHORT 0x0400
575#define RS_MULTICAST 0x0001
576#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
577
578
579/* PHY Types */
580enum {
581 PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
582 PHY_LAN83C180
583};
584
585
586/* PHY Register Addresses (LAN91C111 Internal PHY) */
587
588/* PHY Control Register */
589#define PHY_CNTL_REG 0x00
590#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
591#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
592#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
593#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
594#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
595#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
596#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
597#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
598#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
599
600/* PHY Status Register */
601#define PHY_STAT_REG 0x01
602#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
603#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
604#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
605#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
606#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
607#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
608#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
609#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
610#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
611#define PHY_STAT_LINK 0x0004 /* 1=valid link */
612#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
613#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
614
615/* PHY Identifier Registers */
616#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
617#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
618
619/* PHY Auto-Negotiation Advertisement Register */
620#define PHY_AD_REG 0x04
621#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
622#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
623#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
624#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
625#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
626#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
627#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
628#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
629#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
630
631/* PHY Auto-negotiation Remote End Capability Register */
632#define PHY_RMT_REG 0x05
633/* Uses same bit definitions as PHY_AD_REG */
634
635/* PHY Configuration Register 1 */
636#define PHY_CFG1_REG 0x10
637#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
638#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
639#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
640#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
641#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
642#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
643#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
644#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
645#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
646#define PHY_CFG1_TLVL_MASK 0x003C
647#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
648
649
650/* PHY Configuration Register 2 */
651#define PHY_CFG2_REG 0x11
652#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
653#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
654#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
655#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
656
657/* PHY Status Output (and Interrupt status) Register */
658#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
659#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
660#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
661#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
662#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
663#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
664#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
665#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
666#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
667#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
668#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
669
670/* PHY Interrupt/Status Mask Register */
671#define PHY_MASK_REG 0x13 /* Interrupt Mask */
672/* Uses the same bit definitions as PHY_INT_REG */
673
674
wdenkfe8c2802002-11-03 00:38:21 +0000675/*-------------------------------------------------------------------------
676 . I define some macros to make it easier to do somewhat common
677 . or slightly complicated, repeated tasks.
678 --------------------------------------------------------------------------*/
679
680/* select a register bank, 0 to 3 */
681
682#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
683
684/* this enables an interrupt in the interrupt mask register */
685#define SMC_ENABLE_INT(x) {\
686 unsigned char mask;\
687 SMC_SELECT_BANK(2);\
688 mask = SMC_inb( IM_REG );\
689 mask |= (x);\
690 SMC_outb( mask, IM_REG ); \
691}
692
693/* this disables an interrupt from the interrupt mask register */
694
695#define SMC_DISABLE_INT(x) {\
696 unsigned char mask;\
697 SMC_SELECT_BANK(2);\
698 mask = SMC_inb( IM_REG );\
699 mask &= ~(x);\
700 SMC_outb( mask, IM_REG ); \
701}
702
703/*----------------------------------------------------------------------
704 . Define the interrupts that I want to receive from the card
705 .
706 . I want:
707 . IM_EPH_INT, for nasty errors
708 . IM_RCV_INT, for happy received packets
709 . IM_RX_OVRN_INT, because I have to kick the receiver
710 . IM_MDINT, for PHY Register 18 Status Changes
711 --------------------------------------------------------------------------*/
712#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
713 IM_MDINT)
714
715#endif /* _SMC_91111_H_ */