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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass151b2232015-07-02 18:15:58 -06002/*
3 * Copyright (c) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glass151b2232015-07-02 18:15:58 -06005 */
6
7#ifndef __TPS65090_PMIC_H_
8#define __TPS65090_PMIC_H_
9
10/* I2C device address for TPS65090 PMU */
11#define TPS65090_I2C_ADDR 0x48
12
13/* TPS65090 register addresses */
14enum {
15 REG_IRQ1 = 0,
16 REG_CG_CTRL0 = 4,
17 REG_CG_STATUS1 = 0xa,
18 REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */
19 REG_FET1_CTRL,
20 REG_FET2_CTRL,
21 REG_FET3_CTRL,
22 REG_FET4_CTRL,
23 REG_FET5_CTRL,
24 REG_FET6_CTRL,
25 REG_FET7_CTRL,
26 TPS65090_NUM_REGS,
27};
28
29enum {
30 IRQ1_VBATG = 1 << 3,
31 CG_CTRL0_ENC_MASK = 0x01,
32
33 MAX_FET_NUM = 7,
34 MAX_CTRL_READ_TRIES = 5,
35
36 /* TPS65090 FET_CTRL register values */
37 FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
38 FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
39 FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
40 FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */
41 FET_CTRL_ENFET = 1 << 0, /* Enable FET */
42};
43
44enum {
45 /* Status register fields */
46 TPS65090_ST1_OTC = 1 << 0,
47 TPS65090_ST1_OCC = 1 << 1,
48 TPS65090_ST1_STATE_SHIFT = 4,
49 TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT,
50};
51
52/* Drivers name */
53#define TPS65090_FET_DRIVER "tps65090_fet"
54
55#endif /* __TPS65090_PMIC_H_ */