| wdenk | fef08ee | 2002-10-31 08:57:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef _CPC710_H_ |
| 25 | #define _CPC710_H_ |
| 26 | |
| 27 | /* Revision */ |
| 28 | #define CPC710_TYPE_100 0x80 |
| 29 | #define CPC710_TYPE_100P 0x90 |
| 30 | |
| 31 | /* System control area */ |
| 32 | #define HW_PHYS_SCA 0xff000000 |
| 33 | |
| 34 | #define HW_SCA_CPC0 0x000000 |
| 35 | #define HW_SCA_SDRAM0 0x000000 |
| 36 | #define HW_SCA_DMA0 0x1C0000 |
| 37 | |
| 38 | #define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0) |
| 39 | #define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0) |
| 40 | |
| 41 | #define HW_CPC0_PCICNFR 0x000c |
| 42 | #define HW_CPC0_RSTR 0x0010 |
| 43 | #define HW_CPC0_SPOR 0x00e8 |
| 44 | #define HW_CPC0_UCTL 0x1000 |
| 45 | #define HW_CPC0_SIOC0 0x1020 |
| 46 | #define HW_CPC0_ABCNTL 0x1030 |
| 47 | #define HW_CPC0_SESR 0x1060 |
| 48 | #define HW_CPC0_SEAR 0x1070 |
| 49 | #define HW_CPC0_PGCHP 0x1100 |
| 50 | #define HW_CPC0_RGBAN0 0x1110 |
| 51 | #define HW_CPC0_RGBAN1 0x1120 |
| 52 | |
| 53 | #define HW_CPC0_GPDIR 0x1130 |
| 54 | #define HW_CPC0_GPIN 0x1140 |
| 55 | #define HW_CPC0_GPOUT 0x1150 |
| 56 | |
| 57 | #define HW_CPC0_ATAS 0x1160 |
| 58 | |
| 59 | #define HW_CPC0_PCIBAR 0x200018 |
| 60 | #define HW_CPC0_PCIENB 0x201000 |
| 61 | |
| 62 | #define HW_SDRAM0_MCCR 0x1200 |
| 63 | #define HW_SDRAM0_MESR 0x1220 |
| 64 | #define HW_SDRAM0_MEAR 0x1230 |
| 65 | |
| 66 | #define HW_SDRAM0_MCER0 0x1300 |
| 67 | #define HW_SDRAM0_MCER1 0x1310 |
| 68 | #define HW_SDRAM0_MCER2 0x1320 |
| 69 | #define HW_SDRAM0_MCER3 0x1330 |
| 70 | #define HW_SDRAM0_MCER4 0x1340 |
| 71 | #define HW_SDRAM0_MCER5 0x1350 |
| 72 | #define HW_SDRAM0_MCER6 0x1360 |
| 73 | #define HW_SDRAM0_MCER7 0x1370 |
| 74 | |
| 75 | #define HW_BRIDGE_PCIDG 0xf6120 |
| 76 | #define HW_BRIDGE_INTACK 0xf7700 |
| 77 | #define HW_BRIDGE_PIBAR 0xf7800 |
| 78 | #define HW_BRIDGE_PMBAR 0xf7810 |
| 79 | #define HW_BRIDGE_CRR 0xf7ef0 |
| 80 | #define HW_BRIDGE_PR 0xf7f20 |
| 81 | #define HW_BRIDGE_ACR 0xf7f30 |
| 82 | #define HW_BRIDGE_MSIZE 0xf7f40 |
| 83 | #define HW_BRIDGE_IOSIZE 0xf7f60 |
| 84 | #define HW_BRIDGE_SMBAR 0xf7f80 |
| 85 | #define HW_BRIDGE_SIBAR 0xf7fc0 |
| 86 | #define HW_BRIDGE_CFGADDR 0xf8000 |
| 87 | #define HW_BRIDGE_CFGDATA 0xf8010 |
| 88 | #define HW_BRIDGE_PSSIZE 0xf8100 |
| 89 | #define HW_BRIDGE_BARPS 0xf8120 |
| 90 | #define HW_BRIDGE_PSBAR 0xf8140 |
| 91 | |
| 92 | /* Configuration space registers */ |
| 93 | #define CPC710_BUS_NUMBER 0x40 |
| 94 | #define CPC710_SUB_BUS_NUMBER 0x41 |
| 95 | |
| 96 | #endif |