blob: 791bb8dc47f39db5709a3bbbef61a4c578022d38 [file] [log] [blame]
Vabhav Sharmad90c7ac2019-06-06 12:35:28 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2019 NXP
4 */
5
6#ifndef __LS1046AFRWY_H__
7#define __LS1046AFRWY_H__
8
9#include "ls1046a_common.h"
10
11#define CONFIG_SYS_CLK_FREQ 100000000
12#define CONFIG_DDR_CLK_FREQ 100000000
13
14#define CONFIG_LAYERSCAPE_NS_ACCESS
15
16#define CONFIG_DIMM_SLOTS_PER_CTLR 1
17#define CONFIG_CHIP_SELECTS_PER_CTRL 4
18
19#define CONFIG_SYS_UBOOT_BASE 0x40100000
20
21/* IFC */
22#define CONFIG_FSL_IFC
23/*
24 * NAND Flash Definitions
25 */
26#define CONFIG_NAND_FSL_IFC
27
28#define CONFIG_SYS_NAND_BASE 0x7e800000
29#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
30
31#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
32#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
33 | CSPR_PORT_SIZE_8 \
34 | CSPR_MSEL_NAND \
35 | CSPR_V)
36#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
37#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
38 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
39 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
40 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
41 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
42 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
43 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
44
45#define CONFIG_SYS_NAND_ONFI_DETECTION
46
47#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
48 FTIM0_NAND_TWP(0x18) | \
49 FTIM0_NAND_TWCHT(0x7) | \
50 FTIM0_NAND_TWH(0xa))
51#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
52 FTIM1_NAND_TWBE(0x39) | \
53 FTIM1_NAND_TRR(0xe) | \
54 FTIM1_NAND_TRP(0x18))
55#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
56 FTIM2_NAND_TREH(0xa) | \
57 FTIM2_NAND_TWHRE(0x1e))
58#define CONFIG_SYS_NAND_FTIM3 0x0
59
60#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
61#define CONFIG_SYS_MAX_NAND_DEVICE 1
62#define CONFIG_MTD_NAND_VERIFY_WRITE
63
64#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
65
66/* IFC Timing Params */
67#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
68#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
69#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
70#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
71#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
72#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
73#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
74#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
75
76/* EEPROM */
77#define CONFIG_ID_EEPROM
78#define CONFIG_SYS_I2C_EEPROM_NXID
79#define CONFIG_SYS_EEPROM_BUS_NUM 0
80#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
81#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
82#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
83#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
84#define I2C_RETIMER_ADDR 0x18
85
86/* I2C bus multiplexer */
87#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
88#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
89#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
90
91/* RTC */
92#define RTC
93#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
94#define CONFIG_SYS_RTC_BUS_NUM 0
95
96/*
97 * Environment
98 */
99#define CONFIG_ENV_OVERWRITE
100
101#define CONFIG_SYS_MMC_ENV_DEV 0
102
103#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
104#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
105#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
106
107/* FMan */
108#ifdef CONFIG_SYS_DPAA_FMAN
109#define CONFIG_FMAN_ENET
110
111#define QSGMII_PORT1_PHY_ADDR 0x1c
112#define QSGMII_PORT2_PHY_ADDR 0x1d
113#define QSGMII_PORT3_PHY_ADDR 0x1e
114#define QSGMII_PORT4_PHY_ADDR 0x1f
115
116#define FDT_SEQ_MACADDR_FROM_ENV
117
118#define CONFIG_ETHPRIME "FM1@DTSEC3"
119
120#endif
121
122/* QSPI device */
123#ifdef CONFIG_FSL_QSPI
124#define FSL_QSPI_FLASH_SIZE SZ_64M
125#define FSL_QSPI_FLASH_NUM 1
126#endif
127
128#undef CONFIG_BOOTCOMMAND
129#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
130 "env exists secureboot && esbc_halt;;"
131#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
132 "env exists secureboot && esbc_halt;"
133
134#include <asm/fsl_secure_boot.h>
135
136#endif /* __LS1046AFRWY_H__ */