Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 10 | #include <linux/errno.h> |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 11 | #include <asm/arch/fpga_manager.h> |
| 12 | #include <asm/arch/reset_manager.h> |
| 13 | #include <asm/arch/system_manager.h> |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | /* Timeout count */ |
| 18 | #define FPGA_TIMEOUT_CNT 0x1000000 |
| 19 | |
| 20 | static struct socfpga_fpga_manager *fpgamgr_regs = |
| 21 | (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 22 | |
Tien Fong Chee | 6867e19 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 23 | int fpgamgr_dclkcnt_set(unsigned long cnt) |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 24 | { |
| 25 | unsigned long i; |
| 26 | |
| 27 | /* Clear any existing done status */ |
| 28 | if (readl(&fpgamgr_regs->dclkstat)) |
| 29 | writel(0x1, &fpgamgr_regs->dclkstat); |
| 30 | |
| 31 | /* Write the dclkcnt */ |
| 32 | writel(cnt, &fpgamgr_regs->dclkcnt); |
| 33 | |
| 34 | /* Wait till the dclkcnt done */ |
| 35 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
| 36 | if (!readl(&fpgamgr_regs->dclkstat)) |
| 37 | continue; |
| 38 | |
| 39 | writel(0x1, &fpgamgr_regs->dclkstat); |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | return -ETIMEDOUT; |
| 44 | } |
| 45 | |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 46 | /* Write the RBF data to FPGA Manager */ |
Tien Fong Chee | 6867e19 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 47 | void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 48 | { |
| 49 | uint32_t src = (uint32_t)rbf_data; |
| 50 | uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; |
| 51 | |
| 52 | /* Number of loops for 32-byte long copying. */ |
| 53 | uint32_t loops32 = rbf_size / 32; |
| 54 | /* Number of loops for 4-byte long copying + trailing bytes */ |
| 55 | uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); |
| 56 | |
| 57 | asm volatile( |
| 58 | "1: ldmia %0!, {r0-r7}\n" |
| 59 | " stmia %1!, {r0-r7}\n" |
| 60 | " sub %1, #32\n" |
| 61 | " subs %2, #1\n" |
| 62 | " bne 1b\n" |
Marek Vasut | bfa89d2 | 2015-07-27 22:34:54 +0200 | [diff] [blame] | 63 | " cmp %3, #0\n" |
| 64 | " beq 3f\n" |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 65 | "2: ldr %2, [%0], #4\n" |
| 66 | " str %2, [%1]\n" |
| 67 | " subs %3, #1\n" |
| 68 | " bne 2b\n" |
Marek Vasut | bfa89d2 | 2015-07-27 22:34:54 +0200 | [diff] [blame] | 69 | "3: nop\n" |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 70 | : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : |
| 71 | : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); |
| 72 | } |
| 73 | |