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Stefan Roese5e7abce2010-09-11 09:31:43 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef _PPC405EP_H_
22#define _PPC405EP_H_
23
24#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
25
Stefan Roeseafabb492010-09-12 06:21:37 +020026/* Memory mapped register */
Stefan Roese550650d2010-09-20 16:05:31 +020027#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
28
29#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
30#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
31
32#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
Stefan Roeseafabb492010-09-12 06:21:37 +020033
34/* DCR */
35#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
36#define OCM0_DSARC 0x001a /* OCM D-side address compare */
37#define OCM0_DSCNTL 0x001b /* OCM D-side control */
38#define CPC0_PLLMR0 0x00f0 /* PLL mode register 0 */
39#define CPC0_BOOT 0x00f1 /* Clock status register */
40#define CPC0_CR1 0x00f2 /* Chip Control 1 register */
41#define CPC0_EPCTL 0x00f3 /* EMAC to PHY control register */
42#define CPC0_PLLMR1 0x00f4 /* PLL mode register 1 */
43#define CPC0_UCR 0x00f5 /* UART control register */
44#define CPC0_SRR 0x00f6 /* Soft Reset register */
45#define CPC0_PCI 0x00f9 /* PCI control register */
46
47/* Defines for CPC0_EPCTL register */
48#define CPC0_EPCTL_E0NFE 0x80000000
49#define CPC0_EPCTL_E1NFE 0x40000000
50
51/* Defines for CPC0_PCI Register */
52#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
53#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
54#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
55
56/* Defines for CPC0_BOOR Register */
57#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
58
59/* Bit definitions */
60#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
61#define PLLMR0_CPU_DIV_BYPASS 0x00000000
62#define PLLMR0_CPU_DIV_2 0x00100000
63#define PLLMR0_CPU_DIV_3 0x00200000
64#define PLLMR0_CPU_DIV_4 0x00300000
65
66#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
67#define PLLMR0_CPU_PLB_DIV_1 0x00000000
68#define PLLMR0_CPU_PLB_DIV_2 0x00010000
69#define PLLMR0_CPU_PLB_DIV_3 0x00020000
70#define PLLMR0_CPU_PLB_DIV_4 0x00030000
71
72#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
73#define PLLMR0_OPB_PLB_DIV_1 0x00000000
74#define PLLMR0_OPB_PLB_DIV_2 0x00001000
75#define PLLMR0_OPB_PLB_DIV_3 0x00002000
76#define PLLMR0_OPB_PLB_DIV_4 0x00003000
77
78#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
79#define PLLMR0_EXB_PLB_DIV_2 0x00000000
80#define PLLMR0_EXB_PLB_DIV_3 0x00000100
81#define PLLMR0_EXB_PLB_DIV_4 0x00000200
82#define PLLMR0_EXB_PLB_DIV_5 0x00000300
83
84#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
85#define PLLMR0_MAL_PLB_DIV_1 0x00000000
86#define PLLMR0_MAL_PLB_DIV_2 0x00000010
87#define PLLMR0_MAL_PLB_DIV_3 0x00000020
88#define PLLMR0_MAL_PLB_DIV_4 0x00000030
89
90#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
91#define PLLMR0_PCI_PLB_DIV_1 0x00000000
92#define PLLMR0_PCI_PLB_DIV_2 0x00000001
93#define PLLMR0_PCI_PLB_DIV_3 0x00000002
94#define PLLMR0_PCI_PLB_DIV_4 0x00000003
95
96#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
97#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
98#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
99
100#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
101#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
102#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
103
104/* Defines for CPC0_PLLMR1 Register fields */
105#define PLL_ACTIVE 0x80000000
106#define CPC0_PLLMR1_SSCS 0x80000000
107#define PLL_RESET 0x40000000
108#define CPC0_PLLMR1_PLLR 0x40000000
109/* Feedback multiplier */
110#define PLL_FBKDIV 0x00F00000
111#define CPC0_PLLMR1_FBDV 0x00F00000
112#define PLL_FBKDIV_16 0x00000000
113#define PLL_FBKDIV_1 0x00100000
114#define PLL_FBKDIV_2 0x00200000
115#define PLL_FBKDIV_3 0x00300000
116#define PLL_FBKDIV_4 0x00400000
117#define PLL_FBKDIV_5 0x00500000
118#define PLL_FBKDIV_6 0x00600000
119#define PLL_FBKDIV_7 0x00700000
120#define PLL_FBKDIV_8 0x00800000
121#define PLL_FBKDIV_9 0x00900000
122#define PLL_FBKDIV_10 0x00A00000
123#define PLL_FBKDIV_11 0x00B00000
124#define PLL_FBKDIV_12 0x00C00000
125#define PLL_FBKDIV_13 0x00D00000
126#define PLL_FBKDIV_14 0x00E00000
127#define PLL_FBKDIV_15 0x00F00000
128/* Forward A divisor */
129#define PLL_FWDDIVA 0x00070000
130#define CPC0_PLLMR1_FWDVA 0x00070000
131#define PLL_FWDDIVA_8 0x00000000
132#define PLL_FWDDIVA_7 0x00010000
133#define PLL_FWDDIVA_6 0x00020000
134#define PLL_FWDDIVA_5 0x00030000
135#define PLL_FWDDIVA_4 0x00040000
136#define PLL_FWDDIVA_3 0x00050000
137#define PLL_FWDDIVA_2 0x00060000
138#define PLL_FWDDIVA_1 0x00070000
139/* Forward B divisor */
140#define PLL_FWDDIVB 0x00007000
141#define CPC0_PLLMR1_FWDVB 0x00007000
142#define PLL_FWDDIVB_8 0x00000000
143#define PLL_FWDDIVB_7 0x00001000
144#define PLL_FWDDIVB_6 0x00002000
145#define PLL_FWDDIVB_5 0x00003000
146#define PLL_FWDDIVB_4 0x00004000
147#define PLL_FWDDIVB_3 0x00005000
148#define PLL_FWDDIVB_2 0x00006000
149#define PLL_FWDDIVB_1 0x00007000
150/* PLL tune bits */
151#define PLL_TUNE_MASK 0x000003FF
152#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
153#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
154#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
155#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
156#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
157#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
158#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
159
160/* Defines for CPC0_PLLMR0 Register fields */
161/* CPU divisor */
162#define PLL_CPUDIV 0x00300000
163#define CPC0_PLLMR0_CCDV 0x00300000
164#define PLL_CPUDIV_1 0x00000000
165#define PLL_CPUDIV_2 0x00100000
166#define PLL_CPUDIV_3 0x00200000
167#define PLL_CPUDIV_4 0x00300000
168/* PLB divisor */
169#define PLL_PLBDIV 0x00030000
170#define CPC0_PLLMR0_CBDV 0x00030000
171#define PLL_PLBDIV_1 0x00000000
172#define PLL_PLBDIV_2 0x00010000
173#define PLL_PLBDIV_3 0x00020000
174#define PLL_PLBDIV_4 0x00030000
175/* OPB divisor */
176#define PLL_OPBDIV 0x00003000
177#define CPC0_PLLMR0_OPDV 0x00003000
178#define PLL_OPBDIV_1 0x00000000
179#define PLL_OPBDIV_2 0x00001000
180#define PLL_OPBDIV_3 0x00002000
181#define PLL_OPBDIV_4 0x00003000
182/* EBC divisor */
183#define PLL_EXTBUSDIV 0x00000300
184#define CPC0_PLLMR0_EPDV 0x00000300
185#define PLL_EXTBUSDIV_2 0x00000000
186#define PLL_EXTBUSDIV_3 0x00000100
187#define PLL_EXTBUSDIV_4 0x00000200
188#define PLL_EXTBUSDIV_5 0x00000300
189/* MAL divisor */
190#define PLL_MALDIV 0x00000030
191#define CPC0_PLLMR0_MPDV 0x00000030
192#define PLL_MALDIV_1 0x00000000
193#define PLL_MALDIV_2 0x00000010
194#define PLL_MALDIV_3 0x00000020
195#define PLL_MALDIV_4 0x00000030
196/* PCI divisor */
197#define PLL_PCIDIV 0x00000003
198#define CPC0_PLLMR0_PPFD 0x00000003
199#define PLL_PCIDIV_1 0x00000000
200#define PLL_PCIDIV_2 0x00000001
201#define PLL_PCIDIV_3 0x00000002
202#define PLL_PCIDIV_4 0x00000003
203
204/*
205 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
206 * assuming a 33.3MHz input clock to the 405EP.
207 */
208#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
209 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
210 PLL_MALDIV_1 | PLL_PCIDIV_4)
211#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
212 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
213 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
214
215#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
216 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
217 PLL_MALDIV_1 | PLL_PCIDIV_4)
218#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
219 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
220 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
221#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
222 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
223 PLL_MALDIV_1 | PLL_PCIDIV_4)
224#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
225 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
226 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
227#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
228 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
229 PLL_MALDIV_1 | PLL_PCIDIV_4)
230#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
231 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
232 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
233#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
234 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
235 PLL_MALDIV_1 | PLL_PCIDIV_2)
236#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
237 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
238 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
239#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
240 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
241 PLL_MALDIV_1 | PLL_PCIDIV_3)
242#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
243 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
244 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
245#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
246 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
247 PLL_MALDIV_1 | PLL_PCIDIV_1)
248#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
249 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
250 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
251
Stefan Roese5e7abce2010-09-11 09:31:43 +0200252#endif /* _PPC405EP_H_ */