| wdenk | 074cff0 | 2004-02-24 00:16:43 +0000 | [diff] [blame] | 1 | /********************************************************/ |
| 2 | /* */ |
| 3 | /* Samsung S3C44B0 */ |
| 4 | /* tpu <tapu@371.net> */ |
| 5 | /* */ |
| 6 | /********************************************************/ |
| 7 | #ifndef __ASM_ARCH_HARDWARE_H |
| 8 | #define __ASM_ARCH_HARDWARE_H |
| 9 | |
| 10 | #define REGBASE 0x01c00000 |
| 11 | #define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) |
| 12 | #define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) |
| 13 | #define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) |
| 14 | |
| 15 | |
| 16 | /*****************************/ |
| 17 | /* CPU Wrapper Registers */ |
| 18 | /*****************************/ |
| 19 | |
| 20 | #define SYSCFG REGL(0x000000) |
| 21 | #define NCACHBE0 REGL(0x000004) |
| 22 | #define NCACHBE1 REGL(0x000008) |
| 23 | #define SBUSCON REGL(0x040000) |
| 24 | |
| 25 | /************************************/ |
| 26 | /* Memory Controller Registers */ |
| 27 | /************************************/ |
| 28 | |
| 29 | #define BWSCON REGL(0x080000) |
| 30 | #define BANKCON0 REGL(0x080004) |
| 31 | #define BANKCON1 REGL(0x080008) |
| 32 | #define BANKCON2 REGL(0x08000c) |
| 33 | #define BANKCON3 REGL(0x080010) |
| 34 | #define BANKCON4 REGL(0x080014) |
| 35 | #define BANKCON5 REGL(0x080018) |
| 36 | #define BANKCON6 REGL(0x08001c) |
| 37 | #define BANKCON7 REGL(0x080020) |
| 38 | #define REFRESH REGL(0x080024) |
| 39 | #define BANKSIZE REGL(0x080028) |
| 40 | #define MRSRB6 REGL(0x08002c) |
| 41 | #define MRSRB7 REGL(0x080030) |
| 42 | |
| 43 | /*********************/ |
| 44 | /* UART Registers */ |
| 45 | /*********************/ |
| 46 | |
| 47 | #define ULCON0 REGL(0x100000) |
| 48 | #define ULCON1 REGL(0x104000) |
| 49 | #define UCON0 REGL(0x100004) |
| 50 | #define UCON1 REGL(0x104004) |
| 51 | #define UFCON0 REGL(0x100008) |
| 52 | #define UFCON1 REGL(0x104008) |
| 53 | #define UMCON0 REGL(0x10000c) |
| 54 | #define UMCON1 REGL(0x10400c) |
| 55 | #define UTRSTAT0 REGL(0x100010) |
| 56 | #define UTRSTAT1 REGL(0x104010) |
| 57 | #define UERSTAT0 REGL(0x100014) |
| 58 | #define UERSTAT1 REGL(0x104014) |
| 59 | #define UFSTAT0 REGL(0x100018) |
| 60 | #define UFSTAT1 REGL(0x104018) |
| 61 | #define UMSTAT0 REGL(0x10001c) |
| 62 | #define UMSTAT1 REGL(0x10401c) |
| 63 | #define UTXH0 REGB(0x100020) |
| 64 | #define UTXH1 REGB(0x104020) |
| 65 | #define URXH0 REGB(0x100024) |
| 66 | #define URXH1 REGB(0x104024) |
| 67 | #define UBRDIV0 REGL(0x100028) |
| 68 | #define UBRDIV1 REGL(0x104028) |
| 69 | |
| 70 | /*******************/ |
| 71 | /* SIO Registers */ |
| 72 | /*******************/ |
| 73 | |
| 74 | #define SIOCON REGL(0x114000) |
| 75 | #define SIODAT REGL(0x114004) |
| 76 | #define SBRDR REGL(0x114008) |
| 77 | #define ITVCNT REGL(0x11400c) |
| 78 | #define DCNTZ REGL(0x114010) |
| 79 | |
| 80 | /********************/ |
| 81 | /* IIS Registers */ |
| 82 | /********************/ |
| 83 | |
| 84 | #define IISCON REGL(0x118000) |
| 85 | #define IISMOD REGL(0x118004) |
| 86 | #define IISPSR REGL(0x118008) |
| 87 | #define IISFIFCON REGL(0x11800c) |
| 88 | #define IISFIF REGW(0x118010) |
| 89 | |
| 90 | /**************************/ |
| 91 | /* I/O Ports Registers */ |
| 92 | /**************************/ |
| 93 | |
| 94 | #define PCONA REGL(0x120000) |
| 95 | #define PDATA REGL(0x120004) |
| 96 | #define PCONB REGL(0x120008) |
| 97 | #define PDATB REGL(0x12000c) |
| 98 | #define PCONC REGL(0x120010) |
| 99 | #define PDATC REGL(0x120014) |
| 100 | #define PUPC REGL(0x120018) |
| 101 | #define PCOND REGL(0x12001c) |
| 102 | #define PDATD REGL(0x120020) |
| 103 | #define PUPD REGL(0x120024) |
| 104 | #define PCONE REGL(0x120028) |
| 105 | #define PDATE REGL(0x12002c) |
| 106 | #define PUPE REGL(0x120030) |
| 107 | #define PCONF REGL(0x120034) |
| 108 | #define PDATF REGL(0x120038) |
| 109 | #define PUPF REGL(0x12003c) |
| 110 | #define PCONG REGL(0x120040) |
| 111 | #define PDATG REGL(0x120044) |
| 112 | #define PUPG REGL(0x120048) |
| 113 | #define SPUCR REGL(0x12004c) |
| 114 | #define EXTINT REGL(0x120050) |
| 115 | #define EXTINTPND REGL(0x120054) |
| 116 | |
| 117 | /*********************************/ |
| 118 | /* WatchDog Timers Registers */ |
| 119 | /*********************************/ |
| 120 | |
| 121 | #define WTCON REGL(0x130000) |
| 122 | #define WTDAT REGL(0x130004) |
| 123 | #define WTCNT REGL(0x130008) |
| 124 | |
| 125 | /*********************************/ |
| 126 | /* A/D Converter Registers */ |
| 127 | /*********************************/ |
| 128 | |
| 129 | #define ADCCON REGL(0x140000) |
| 130 | #define ADCPSR REGL(0x140004) |
| 131 | #define ADCDAT REGL(0x140008) |
| 132 | |
| 133 | /***************************/ |
| 134 | /* PWM Timer Registers */ |
| 135 | /***************************/ |
| 136 | |
| 137 | #define TCFG0 REGL(0x150000) |
| 138 | #define TCFG1 REGL(0x150004) |
| 139 | #define TCON REGL(0x150008) |
| 140 | #define TCNTB0 REGL(0x15000c) |
| 141 | #define TCMPB0 REGL(0x150010) |
| 142 | #define TCNTO0 REGL(0x150014) |
| 143 | #define TCNTB1 REGL(0x150018) |
| 144 | #define TCMPB1 REGL(0x15001c) |
| 145 | #define TCNTO1 REGL(0x150020) |
| 146 | #define TCNTB2 REGL(0x150024) |
| 147 | #define TCMPB2 REGL(0x150028) |
| 148 | #define TCNTO2 REGL(0x15002c) |
| 149 | #define TCNTB3 REGL(0x150030) |
| 150 | #define TCMPB3 REGL(0x150034) |
| 151 | #define TCNTO3 REGL(0x150038) |
| 152 | #define TCNTB4 REGL(0x15003c) |
| 153 | #define TCMPB4 REGL(0x150040) |
| 154 | #define TCNTO4 REGL(0x150044) |
| 155 | #define TCNTB5 REGL(0x150048) |
| 156 | #define TCNTO5 REGL(0x15004c) |
| 157 | |
| 158 | /*********************/ |
| 159 | /* IIC Registers */ |
| 160 | /*********************/ |
| 161 | |
| 162 | #define IICCON REGL(0x160000) |
| 163 | #define IICSTAT REGL(0x160004) |
| 164 | #define IICADD REGL(0x160008) |
| 165 | #define IICDS REGL(0x16000c) |
| 166 | |
| 167 | /*********************/ |
| 168 | /* RTC Registers */ |
| 169 | /*********************/ |
| 170 | |
| 171 | #define RTCCON REGB(0x170040) |
| 172 | #define RTCALM REGB(0x170050) |
| 173 | #define ALMSEC REGB(0x170054) |
| 174 | #define ALMMIN REGB(0x170058) |
| 175 | #define ALMHOUR REGB(0x17005c) |
| 176 | #define ALMDAY REGB(0x170060) |
| 177 | #define ALMMON REGB(0x170064) |
| 178 | #define ALMYEAR REGB(0x170068) |
| 179 | #define RTCRST REGB(0x17006c) |
| 180 | #define BCDSEC REGB(0x170070) |
| 181 | #define BCDMIN REGB(0x170074) |
| 182 | #define BCDHOUR REGB(0x170078) |
| 183 | #define BCDDAY REGB(0x17007c) |
| 184 | #define BCDDATE REGB(0x170080) |
| 185 | #define BCDMON REGB(0x170084) |
| 186 | #define BCDYEAR REGB(0x170088) |
| 187 | #define TICINT REGB(0x17008c) |
| 188 | |
| 189 | /*********************************/ |
| 190 | /* Clock & Power Registers */ |
| 191 | /*********************************/ |
| 192 | |
| 193 | #define PLLCON REGL(0x180000) |
| 194 | #define CLKCON REGL(0x180004) |
| 195 | #define CLKSLOW REGL(0x180008) |
| 196 | #define LOCKTIME REGL(0x18000c) |
| 197 | |
| 198 | /**************************************/ |
| 199 | /* Interrupt Controller Registers */ |
| 200 | /**************************************/ |
| 201 | |
| 202 | #define INTCON REGL(0x200000) |
| 203 | #define INTPND REGL(0x200004) |
| 204 | #define INTMOD REGL(0x200008) |
| 205 | #define INTMSK REGL(0x20000c) |
| 206 | #define I_PSLV REGL(0x200010) |
| 207 | #define I_PMST REGL(0x200014) |
| 208 | #define I_CSLV REGL(0x200018) |
| 209 | #define I_CMST REGL(0x20001c) |
| 210 | #define I_ISPR REGL(0x200020) |
| 211 | #define I_ISPC REGL(0x200024) |
| 212 | #define F_ISPR REGL(0x200038) |
| 213 | #define F_ISPC REGL(0x20003c) |
| 214 | |
| 215 | /********************************/ |
| 216 | /* LCD Controller Registers */ |
| 217 | /********************************/ |
| 218 | |
| 219 | #define LCDCON1 REGL(0x300000) |
| 220 | #define LCDCON2 REGL(0x300004) |
| 221 | #define LCDSADDR1 REGL(0x300008) |
| 222 | #define LCDSADDR2 REGL(0x30000c) |
| 223 | #define LCDSADDR3 REGL(0x300010) |
| 224 | #define REDLUT REGL(0x300014) |
| 225 | #define GREENLUT REGL(0x300018) |
| 226 | #define BLUELUT REGL(0x30001c) |
| 227 | #define DP1_2 REGL(0x300020) |
| 228 | #define DP4_7 REGL(0x300024) |
| 229 | #define DP3_5 REGL(0x300028) |
| 230 | #define DP2_3 REGL(0x30002c) |
| 231 | #define DP5_7 REGL(0x300030) |
| 232 | #define DP3_4 REGL(0x300034) |
| 233 | #define DP4_5 REGL(0x300038) |
| 234 | #define DP6_7 REGL(0x30003c) |
| 235 | #define LCDCON3 REGL(0x300040) |
| 236 | #define DITHMODE REGL(0x300044) |
| 237 | |
| 238 | /*********************/ |
| 239 | /* DMA Registers */ |
| 240 | /*********************/ |
| 241 | |
| 242 | #define ZDCON0 REGL(0x280000) |
| 243 | #define ZDISRC0 REGL(0x280004) |
| 244 | #define ZDIDES0 REGL(0x280008) |
| 245 | #define ZDICNT0 REGL(0x28000c) |
| 246 | #define ZDCSRC0 REGL(0x280010) |
| 247 | #define ZDCDES0 REGL(0x280014) |
| 248 | #define ZDCCNT0 REGL(0x280018) |
| 249 | |
| 250 | #define ZDCON1 REGL(0x280020) |
| 251 | #define ZDISRC1 REGL(0x280024) |
| 252 | #define ZDIDES1 REGL(0x280028) |
| 253 | #define ZDICNT1 REGL(0x28002c) |
| 254 | #define ZDCSRC1 REGL(0x280030) |
| 255 | #define ZDCDES1 REGL(0x280034) |
| 256 | #define ZDCCNT1 REGL(0x280038) |
| 257 | |
| 258 | #define BDCON0 REGL(0x380000) |
| 259 | #define BDISRC0 REGL(0x380004) |
| 260 | #define BDIDES0 REGL(0x380008) |
| 261 | #define BDICNT0 REGL(0x38000c) |
| 262 | #define BDCSRC0 REGL(0x380010) |
| 263 | #define BDCDES0 REGL(0x380014) |
| 264 | #define BDCCNT0 REGL(0x380018) |
| 265 | |
| 266 | #define BDCON1 REGL(0x380020) |
| 267 | #define BDISRC1 REGL(0x380024) |
| 268 | #define BDIDES1 REGL(0x380028) |
| 269 | #define BDICNT1 REGL(0x38002c) |
| 270 | #define BDCSRC1 REGL(0x380030) |
| 271 | #define BDCDES1 REGL(0x380034) |
| 272 | #define BDCCNT1 REGL(0x380038) |
| 273 | |
| 274 | |
| 275 | #define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) |
| 276 | #define INT_ENABLE(n) INTMSK &= ~(1<<(n)) |
| 277 | #define INT_DISABLE(n) INTMSK |= (1<<(n)) |
| 278 | |
| 279 | #define HARD_RESET_NOW() |
| 280 | |
| 281 | #endif /* __ASM_ARCH_HARDWARE_H */ |