blob: 753c8d2435280531233431e7f5915b22962b5378 [file] [log] [blame]
wdenkea66bc82004-04-15 23:23:39 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * 2004 (c) MontaVista Software, Inc.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
Ben Warren1ab70f62009-12-14 16:30:39 -080028#include <netdev.h>
wdenkea66bc82004-04-15 23:23:39 +000029#include <SA-1100.h>
30
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
32
wdenkea66bc82004-04-15 23:23:39 +000033/* ------------------------------------------------------------------------- */
34
35/*
36 * Board dependent initialisation
37 */
38
39#define ECOR 0x8000
40#define ECOR_RESET 0x80
41#define ECOR_LEVEL_IRQ 0x40
42#define ECOR_WR_ATTRIB 0x04
43#define ECOR_ENABLE 0x01
44
45#define ECSR 0x8002
46#define ECSR_IOIS8 0x20
47#define ECSR_PWRDWN 0x04
48#define ECSR_INT 0x02
49#define SMC_IO_SHIFT 2
Wolfgang Denk53677ef2008-05-20 16:00:29 +020050#define NCR_0 (*((volatile u_char *)(0x100000a0)))
wdenkea66bc82004-04-15 23:23:39 +000051#define NCR_ENET_OSC_EN (1<<3)
52
53static inline u8
54readb(volatile u8 * p)
55{
56 return *p;
57}
58
59static inline void
60writeb(u8 v, volatile u8 * p)
61{
62 *p = v;
63}
64
65static void
66smc_init(void)
67{
68 u8 ecor;
69 u8 ecsr;
70 volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
71
72 NCR_0 |= NCR_ENET_OSC_EN;
73 udelay(100);
74
75 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
76 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
77 udelay(100);
78
79 /*
80 * The device will ignore all writes to the enable bit while
81 * reset is asserted, even if the reset bit is cleared in the
82 * same write. Must clear reset first, then enable the device.
83 */
84 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
85 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
86
87 /*
88 * Set the appropriate byte/word mode.
89 */
90 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
91 ecsr |= ECSR_IOIS8;
92 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
93 udelay(100);
94}
95
96static void
97neponset_init(void)
98{
99 smc_init();
100}
101
102int
103board_init(void)
104{
wdenk731215e2004-10-10 18:41:04 +0000105 gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
wdenkea66bc82004-04-15 23:23:39 +0000106 gd->bd->bi_boot_params = 0xc0000100;
107
108 neponset_init();
109
110 return 0;
111}
112
113int
114dram_init(void)
115{
wdenkea66bc82004-04-15 23:23:39 +0000116 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
117 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
118
119 return (0);
120}
Ben Warren1ab70f62009-12-14 16:30:39 -0800121
122#ifdef CONFIG_CMD_NET
123int board_eth_init(bd_t *bis)
124{
125 int rc = 0;
126#ifdef CONFIG_LAN91C96
127 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
128#endif
129 return rc;
130}
131#endif