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wdenkdb01a2e2004-04-15 23:14:49 +00001/*------------------------------------------------------------------------+ */
2/* */
Josh Boyer31773492009-08-07 13:53:20 -04003/* This source code is dual-licensed. You may use it under the terms */
4/* of the GNU General Public License version 2, or under the license */
5/* below. */
6/* */
wdenkdb01a2e2004-04-15 23:14:49 +00007/* This source code has been made available to you by IBM on an AS-IS */
8/* basis. Anyone receiving this source is licensed under IBM */
9/* copyrights to use it in any way he or she deems fit, including */
10/* copying it, modifying it, compiling it, and redistributing it either */
11/* with or without modifications. No license under IBM patents or */
12/* patent applications is to be implied by the copyright license. */
13/* */
14/* Any user of this software should understand that IBM cannot provide */
15/* technical support for this software and will not be responsible for */
16/* any consequences resulting from the use of this software. */
17/* */
18/* Any person who transfers this source code or any derivative work */
19/* must include the IBM copyright notice, this paragraph, and the */
20/* preceding two paragraphs in the transferred software. */
21/* */
22/* COPYRIGHT I B M CORPORATION 1995 */
23/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
24/*------------------------------------------------------------------------- */
25
26/*------------------------------------------------------------------------- */
27/* Function: ext_bus_cntlr_init */
28/* Description: Initializes the External Bus Controller for the external */
29/* peripherals. IMPORTANT: For pass1 this code must run from */
30/* cache since you can not reliably change a peripheral banks */
31/* timing register (pbxap) while running code from that bank. */
32/* For ex., since we are running from ROM on bank 0, we can NOT */
33/* execute the code that modifies bank 0 timings from ROM, so */
34/* we run it from cache. */
35/* */
36/* */
37/* The layout for the PEI JSE board: */
38/* Bank 0 - Flash and SRAM */
39/* Bank 1 - SystemACE */
40/* Bank 2 - not used */
41/* Bank 3 - not used */
42/* Bank 4 - not used */
43/* Bank 5 - not used */
44/* Bank 6 - not used */
45/* Bank 7 - not used */
46/*------------------------------------------------------------------------- */
Stefan Roeseb36df562010-09-09 19:18:00 +020047#include <asm/ppc4xx.h>
wdenkdb01a2e2004-04-15 23:14:49 +000048
49#include <ppc_asm.tmpl>
50#include <ppc_defs.h>
51
52#include <asm/cache.h>
53#include <asm/mmu.h>
54
wdenkdb01a2e2004-04-15 23:14:49 +000055 .globl ext_bus_cntlr_init
56ext_bus_cntlr_init:
57 mflr r4 /* save link register */
58 bl ..getAddr
59..getAddr:
60 mflr r3 /* get address of ..getAddr */
61 mtlr r4 /* restore link register */
62 addi r4,0,14 /* set ctr to 10; used to prefetch */
63 mtctr r4 /* 10 cache lines to fit this function */
64 /* in cache (gives us 8x10=80 instrctns) */
65..ebcloop:
66 icbt r0,r3 /* prefetch cache line for addr in r3 */
67 addi r3,r3,32 /* move to next cache line */
68 bdnz ..ebcloop /* continue for 10 cache lines */
69
70 /*----------------------------------------------------------------- */
71 /* Delay to ensure all accesses to ROM are complete before changing */
72 /* bank 0 timings. 200usec should be enough. */
73 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
74 /*----------------------------------------------------------------- */
75 addis r3,0,0x0
76 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
77 mtctr r3
78..spinlp:
79 bdnz ..spinlp /* spin loop */
80
81 /*----------------------------------------------------------------- */
82 /* Memory Bank 0 (Flash) initialization */
83 /*----------------------------------------------------------------- */
84
Stefan Roesed1c3b272009-09-09 16:25:29 +020085 addi r4,0,PB1AP
86 mtdcr EBC0_CFGADDR,r4
wdenkdb01a2e2004-04-15 23:14:49 +000087 addis r4,0,0x9B01
88 ori r4,r4,0x5480
Stefan Roesed1c3b272009-09-09 16:25:29 +020089 mtdcr EBC0_CFGDATA,r4
wdenkdb01a2e2004-04-15 23:14:49 +000090
Stefan Roesed1c3b272009-09-09 16:25:29 +020091 addi r4,0,PB0CR
92 mtdcr EBC0_CFGADDR,r4
wdenkdb01a2e2004-04-15 23:14:49 +000093 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
94 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
Stefan Roesed1c3b272009-09-09 16:25:29 +020095 mtdcr EBC0_CFGDATA,r4
wdenkdb01a2e2004-04-15 23:14:49 +000096
97 blr