blob: 5638321903a7bf5b697ec8ac49dbc9b81ca2e36a [file] [log] [blame]
Lokesh Vutla00b34e92018-11-02 19:51:09 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
Praneeth Bajjuria665cb12020-05-07 22:35:56 -05003 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 * This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
Lokesh Vutla00b34e92018-11-02 19:51:09 +05305 * http://www.ti.com/lit/pdf/spracj0
6 * Configuration Parameters
7 * Memory Type: DDR4
James Doublesin34f27b22019-10-07 14:04:27 +05308 * Data Rate: 1600 MT/s
Lokesh Vutla00b34e92018-11-02 19:51:09 +05309 * ECC Enabled: No
James Doublesin34f27b22019-10-07 14:04:27 +053010 * Data Width: 32 bits
Lokesh Vutla00b34e92018-11-02 19:51:09 +053011 */
12#define DDR_PLL_FREQUENCY 400000000
James Doublesin34f27b22019-10-07 14:04:27 +053013#define DDRSS_V2H_CTL_REG 0x000073FF
Lokesh Vutla00b34e92018-11-02 19:51:09 +053014#define DDRCTL_MSTR 0x41040010
15#define DDRCTL_RFSHCTL0 0x00210070
16#define DDRCTL_ECCCFG0 0x00000000
17#define DDRCTL_RFSHTMG 0x0061008C
18#define DDRCTL_CRCPARCTL0 0x00008000
19#define DDRCTL_CRCPARCTL1 0x1A000000
20#define DDRCTL_CRCPARCTL2 0x0048051E
21#define DDRCTL_INIT0 0x400100C4
22#define DDRCTL_INIT1 0x004F0000
23#define DDRCTL_INIT3 0x02140501
24#define DDRCTL_INIT4 0x00000020
25#define DDRCTL_INIT5 0x00100000
26#define DDRCTL_INIT6 0x00000480
Praneeth Bajjuria665cb12020-05-07 22:35:56 -050027#define DDRCTL_INIT7 0x00000497
Lokesh Vutla00b34e92018-11-02 19:51:09 +053028#define DDRCTL_DRAMTMG0 0x0C0A1B0D
29#define DDRCTL_DRAMTMG1 0x00030313
30#define DDRCTL_DRAMTMG2 0x0506050A
31#define DDRCTL_DRAMTMG3 0x0000400C
32#define DDRCTL_DRAMTMG4 0x06020206
33#define DDRCTL_DRAMTMG5 0x04040302
34#define DDRCTL_DRAMTMG6 0x00000004
35#define DDRCTL_DRAMTMG7 0x00000404
Praneeth Bajjuria665cb12020-05-07 22:35:56 -050036#define DDRCTL_DRAMTMG8 0x03030C05
Lokesh Vutla00b34e92018-11-02 19:51:09 +053037#define DDRCTL_DRAMTMG9 0x00020208
38#define DDRCTL_DRAMTMG10 0x001C180A
Praneeth Bajjuria665cb12020-05-07 22:35:56 -050039#define DDRCTL_DRAMTMG11 0x1106010E
Lokesh Vutla00b34e92018-11-02 19:51:09 +053040#define DDRCTL_DRAMTMG12 0x00020008
41#define DDRCTL_DRAMTMG13 0x0B100002
42#define DDRCTL_DRAMTMG14 0x00000000
43#define DDRCTL_DRAMTMG15 0x0000003F
44#define DDRCTL_DRAMTMG17 0x00500028
45#define DDRCTL_ZQCTL0 0x21000040
46#define DDRCTL_ZQCTL1 0x0202FAF0
47#define DDRCTL_DFITMG0 0x04888206
48#define DDRCTL_DFITMG1 0x000A0606
49#define DDRCTL_DFITMG2 0x00000604
50#define DDRCTL_DFIMISC 0x00000001
James Doublesin34f27b22019-10-07 14:04:27 +053051#define DDRCTL_ADDRMAP0 0x0000001F
Lokesh Vutla00b34e92018-11-02 19:51:09 +053052#define DDRCTL_ADDRMAP1 0x003F0808
53#define DDRCTL_ADDRMAP2 0x00000000
54#define DDRCTL_ADDRMAP3 0x00000000
55#define DDRCTL_ADDRMAP4 0x00001F1F
56#define DDRCTL_ADDRMAP5 0x08080808
57#define DDRCTL_ADDRMAP6 0x08080808
58#define DDRCTL_ADDRMAP7 0x00000F0F
59#define DDRCTL_ADDRMAP8 0x00000A0A
60#define DDRCTL_ADDRMAP9 0x00000000
61#define DDRCTL_ADDRMAP10 0x00000000
62#define DDRCTL_ADDRMAP11 0x001F1F00
63#define DDRCTL_DQMAP0 0x00000000
64#define DDRCTL_DQMAP1 0x00000000
65#define DDRCTL_DQMAP4 0x00000000
66#define DDRCTL_DQMAP5 0x00000000
67#define DDRCTL_PWRCTL 0x00000000
68#define DDRCTL_RANKCTL 0x00000000
69#define DDRCTL_ODTCFG 0x0600060C
70#define DDRCTL_ODTMAP 0x00000001
71#define DDRPHY_PGCR0 0x07001E00
72#define DDRPHY_PGCR1 0x020046C0
73#define DDRPHY_PGCR2 0x00F0BFE0
74#define DDRPHY_PGCR3 0x55AA0080
75#define DDRPHY_PGCR6 0x00013001
76#define DDRPHY_PTR2 0x00083DEF
77#define DDRPHY_PTR3 0x00061A80
78#define DDRPHY_PTR4 0x00000120
79#define DDRPHY_PTR5 0x00027100
80#define DDRPHY_PTR6 0x04000320
81#define DDRPHY_PLLCR0 0x021c4000
82#define DDRPHY_DXCCR 0x00000038
83#define DDRPHY_DSGCR 0x02A0C129
84#define DDRPHY_DCR 0x0000040C
85#define DDRPHY_DTPR0 0x041A0B06
86#define DDRPHY_DTPR1 0x28140000
Praneeth Bajjuria665cb12020-05-07 22:35:56 -050087#define DDRPHY_DTPR2 0x0034E300
88#define DDRPHY_DTPR3 0x02800800
Lokesh Vutla00b34e92018-11-02 19:51:09 +053089#define DDRPHY_DTPR4 0x31180805
90#define DDRPHY_DTPR5 0x00250B06
91#define DDRPHY_DTPR6 0x00000505
92#define DDRPHY_ZQCR 0x008A2A58
James Doublesin34f27b22019-10-07 14:04:27 +053093#define DDRPHY_ZQ0PR0 0x000077DD
Praneeth Bajjuria665cb12020-05-07 22:35:56 -050094#define DDRPHY_ZQ1PR0 0x00007799
Lokesh Vutla00b34e92018-11-02 19:51:09 +053095#define DDRPHY_MR0 0x00000214
96#define DDRPHY_MR1 0x00000501
97#define DDRPHY_MR2 0x00000000
98#define DDRPHY_MR3 0x00000020
99#define DDRPHY_MR4 0x00000000
100#define DDRPHY_MR5 0x00000480
Praneeth Bajjuria665cb12020-05-07 22:35:56 -0500101#define DDRPHY_MR6 0x00000497
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530102#define DDRPHY_MR11 0x00000000
103#define DDRPHY_MR12 0x00000000
104#define DDRPHY_MR13 0x00000000
105#define DDRPHY_MR14 0x00000000
106#define DDRPHY_MR22 0x00000000
Praneeth Bajjuria665cb12020-05-07 22:35:56 -0500107#define DDRPHY_VTCR0 0xF3C32017
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530108#define DDRPHY_DX8SL0PLLCR0 0x021c4000
109#define DDRPHY_DX8SL1PLLCR0 0x021c4000
110#define DDRPHY_DX8SL2PLLCR0 0x021c4000
111#define DDRPHY_DTCR0 0x8000B1C7
112#define DDRPHY_DTCR1 0x00010236
Praneeth Bajjuria665cb12020-05-07 22:35:56 -0500113#define DDRPHY_ACIOCR0 0xF0070000
James Doublesin34f27b22019-10-07 14:04:27 +0530114#define DDRPHY_ACIOCR3 0x00000001
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530115#define DDRPHY_ACIOCR5 0x04800000
116#define DDRPHY_IOVCR0 0x0F0C0C0C
117#define DDRPHY_DX0GCR0 0x00000000
118#define DDRPHY_DX0GCR1 0x00000000
119#define DDRPHY_DX0GCR2 0x00000000
120#define DDRPHY_DX0GCR3 0x00000000
121#define DDRPHY_DX1GCR0 0x00000000
122#define DDRPHY_DX1GCR1 0x00000000
123#define DDRPHY_DX1GCR2 0x00000000
124#define DDRPHY_DX1GCR3 0x00000000
125#define DDRPHY_DX2GCR0 0x40700204
126#define DDRPHY_DX2GCR1 0x00007FFF
127#define DDRPHY_DX2GCR2 0x00000000
128#define DDRPHY_DX2GCR3 0xFFC0010B
129#define DDRPHY_DX3GCR0 0x40700204
130#define DDRPHY_DX3GCR1 0x00007FFF
131#define DDRPHY_DX3GCR2 0x00000000
132#define DDRPHY_DX3GCR3 0xFFC0010B
133#define DDRPHY_DX4GCR0 0x40703220
134#define DDRPHY_DX4GCR1 0x55556000
135#define DDRPHY_DX4GCR2 0xAAAA0000
136#define DDRPHY_DX4GCR3 0xFFE18587
137#define DDRPHY_DX0GCR4 0x0E00B03C
138#define DDRPHY_DX1GCR4 0x0E00B03C
139#define DDRPHY_DX2GCR4 0x0E00B03C
140#define DDRPHY_DX3GCR4 0x0E00B03C
141#define DDRPHY_DX4GCR4 0x0E00B03C
142#define DDRPHY_PGCR5 0x01010004
143#define DDRPHY_DX0GCR5 0x00000049
144#define DDRPHY_DX1GCR5 0x00000049
145#define DDRPHY_DX2GCR5 0x00000049
146#define DDRPHY_DX3GCR5 0x00000049
147#define DDRPHY_DX4GCR5 0x00000049
148#define DDRPHY_DX0GTR0 0x00020002
149#define DDRPHY_DX1GTR0 0x00020002
150#define DDRPHY_DX2GTR0 0x00020002
151#define DDRPHY_DX3GTR0 0x00020002
152#define DDRPHY_DX4GTR0 0x00020002
153#define DDRPHY_ODTCR 0x00010000
James Doublesin34f27b22019-10-07 14:04:27 +0530154#define DDRPHY_DX8SL0IOCR 0x74800000
155#define DDRPHY_DX8SL1IOCR 0x74800000
156#define DDRPHY_DX8SL2IOCR 0x74800000
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530157#define DDRPHY_DX8SL0DXCTL2 0x00141830
158#define DDRPHY_DX8SL1DXCTL2 0x00141830
159#define DDRPHY_DX8SL2DXCTL2 0x00141830
Praneeth Bajjuria665cb12020-05-07 22:35:56 -0500160#define DDRPHY_DX8SL0DQSCTL 0x01264300
161#define DDRPHY_DX8SL1DQSCTL 0x01264300
162#define DDRPHY_DX8SL2DQSCTL 0x01264300