blob: 47beb86da3244e21a275a8c3b47a6f22c606edd8 [file] [log] [blame]
Bin Meng828d9af2015-02-02 22:35:27 +08001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Bin Meng20c34112015-02-05 23:42:28 +08008#include <errno.h>
9#include <fdtdec.h>
Bin Meng2fc2b832015-10-12 01:30:42 -070010#include <malloc.h>
11#include <asm/mrccache.h>
Bin Mengc6d47052015-09-14 00:07:41 -070012#include <asm/mtrr.h>
Bin Meng828d9af2015-02-02 22:35:27 +080013#include <asm/post.h>
Bin Meng20c34112015-02-05 23:42:28 +080014#include <asm/arch/mrc.h>
Bin Mengc6d47052015-09-14 00:07:41 -070015#include <asm/arch/msg_port.h>
Bin Meng828d9af2015-02-02 22:35:27 +080016#include <asm/arch/quark.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
Bin Meng2fc2b832015-10-12 01:30:42 -070020static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
21{
22 struct mrc_data_container *cache;
23 struct mrc_region entry;
24 int ret;
25
26 ret = mrccache_get_region(NULL, &entry);
27 if (ret)
28 return ret;
29
30 cache = mrccache_find_current(&entry);
31 if (!cache)
32 return -ENOENT;
33
34 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
35 cache->data, cache->data_size, cache->checksum);
36
37 /* copy mrc cache to the mrc_params */
38 memcpy(&mrc_params->timings, cache->data, cache->data_size);
39
40 return 0;
41}
42
Bin Meng20c34112015-02-05 23:42:28 +080043static int mrc_configure_params(struct mrc_params *mrc_params)
44{
45 const void *blob = gd->fdt_blob;
46 int node;
47 int mrc_flags;
48
49 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
50 if (node < 0) {
51 debug("%s: Cannot find MRC node\n", __func__);
52 return -EINVAL;
53 }
54
Bin Meng2fc2b832015-10-12 01:30:42 -070055#ifdef CONFIG_ENABLE_MRC_CACHE
56 mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
57 if (mrc_params->boot_mode)
58 mrc_params->boot_mode = BM_COLD;
59 else
60 mrc_params->boot_mode = BM_FAST;
61#else
Bin Meng20c34112015-02-05 23:42:28 +080062 mrc_params->boot_mode = BM_COLD;
Bin Meng2fc2b832015-10-12 01:30:42 -070063#endif
Bin Meng20c34112015-02-05 23:42:28 +080064
65 /*
66 * TODO:
67 *
68 * We need determine ECC by pin strap state
69 *
70 * Disable ECC by default for now
71 */
72 mrc_params->ecc_enables = 0;
73
74 mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
75 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
76 mrc_params->scrambling_enables = 1;
77 else
78 mrc_params->scrambling_enables = 0;
79
80 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
81 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
82 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
83
84 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
85 mrc_params->channel_enables = fdtdec_get_int(blob, node,
86 "chan-mask", 0);
87 mrc_params->channel_width = fdtdec_get_int(blob, node,
88 "chan-width", 0);
89 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
90
91 mrc_params->refresh_rate = fdtdec_get_int(blob, node,
92 "refresh-rate", 0);
93 mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
94 "sr-temp-range", 0);
95 mrc_params->ron_value = fdtdec_get_int(blob, node,
96 "ron-value", 0);
97 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
98 "rtt-nom-value", 0);
99 mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
100 "rd-odt-value", 0);
101
102 mrc_params->params.density = fdtdec_get_int(blob, node,
103 "dram-density", 0);
104 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
105 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
106 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
107 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
108 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
109
110 debug("MRC dram_width %d\n", mrc_params->dram_width);
111 debug("MRC rank_enables %d\n", mrc_params->rank_enables);
112 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
113 debug("MRC flags: %s\n",
114 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
115
116 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
117 mrc_params->params.density, mrc_params->params.cl,
118 mrc_params->params.ras, mrc_params->params.wtr,
119 mrc_params->params.rrd, mrc_params->params.faw);
120
121 return 0;
122}
123
Bin Meng828d9af2015-02-02 22:35:27 +0800124int dram_init(void)
125{
Bin Meng20c34112015-02-05 23:42:28 +0800126 struct mrc_params mrc_params;
Bin Meng2fc2b832015-10-12 01:30:42 -0700127#ifdef CONFIG_ENABLE_MRC_CACHE
128 char *cache;
129#endif
Bin Meng20c34112015-02-05 23:42:28 +0800130 int ret;
131
132 memset(&mrc_params, 0, sizeof(struct mrc_params));
133 ret = mrc_configure_params(&mrc_params);
134 if (ret)
135 return ret;
136
137 /* Set up the DRAM by calling the memory reference code */
138 mrc_init(&mrc_params);
139 if (mrc_params.status)
140 return -EIO;
141
142 gd->ram_size = mrc_params.mem_size;
Bin Meng828d9af2015-02-02 22:35:27 +0800143 post_code(POST_DRAM);
144
Bin Mengc6d47052015-09-14 00:07:41 -0700145 /* variable range MTRR#2: RAM area */
146 disable_caches();
147 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
148 0 | MTRR_TYPE_WRBACK);
149 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
150 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
151 enable_caches();
152
Bin Meng2fc2b832015-10-12 01:30:42 -0700153#ifdef CONFIG_ENABLE_MRC_CACHE
154 cache = malloc(sizeof(struct mrc_timings));
155 if (cache) {
156 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
157 gd->arch.mrc_output = cache;
158 gd->arch.mrc_output_len = sizeof(struct mrc_timings);
159 }
160#endif
161
Bin Meng828d9af2015-02-02 22:35:27 +0800162 return 0;
163}
164
Simon Glass76b00ac2017-03-31 08:40:32 -0600165int dram_init_banksize(void)
Bin Meng828d9af2015-02-02 22:35:27 +0800166{
167 gd->bd->bi_dram[0].start = 0;
168 gd->bd->bi_dram[0].size = gd->ram_size;
Simon Glass76b00ac2017-03-31 08:40:32 -0600169
170 return 0;
Bin Meng828d9af2015-02-02 22:35:27 +0800171}
172
173/*
174 * This function looks for the highest region of memory lower than 4GB which
175 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
176 * It overrides the default implementation found elsewhere which simply
177 * picks the end of ram, wherever that may be. The location of the stack,
178 * the relocation address, and how far U-Boot is moved by relocation are
179 * set in the global data structure.
180 */
181ulong board_get_usable_ram_top(ulong total_size)
182{
183 return gd->ram_size;
184}