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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7ce85318cfff5fd82a059131761559cba7fef309 / . / arch / x86 / dts / broadwell_som-6896.dts
blob: 39661990853b32bea83095b2383cc9bdf602141b [file] [log] [blame]
George McCollistere0ae6482015-10-21 08:05:33 -0500[diff] [blame]1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4/include/ "serial.dtsi"
5/include/ "rtc.dtsi"
Bin Meng80af3982015-11-13 00:11:22 -0800[diff] [blame]6/include/ "tsc_timer.dtsi"
Bin Meng2d3c5732016-10-09 04:14:18 -0700[diff] [blame]7/include/ "coreboot_fb.dtsi"
George McCollistere0ae6482015-10-21 08:05:33 -0500[diff] [blame]8
9/ {
10 model = "Advantech SOM-6896";
11 compatible = "advantech,som-6896", "intel,broadwell";
12
13 aliases {
Bin Meng81aaa3d2016-01-27 00:56:34 -0800[diff] [blame]14 spi0 = &spi;
George McCollistere0ae6482015-10-21 08:05:33 -0500[diff] [blame]15 };
16
17 config {
18 silent_console = <0>;
19 };
20
21 chosen {
22 stdout-path = "/serial";
23 };
24
25 pci {
26 compatible = "pci-x86";
27 #address-cells = <3>;
28 #size-cells = <2>;
29 u-boot,dm-pre-reloc;
30 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
31 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
32 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
George McCollistere0ae6482015-10-21 08:05:33 -0500[diff] [blame]33
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]34 pch@1f,0 {
35 reg = <0x0000f800 0 0 0 0>;
36 compatible = "intel,pch9";
37
Bin Meng81aaa3d2016-01-27 00:56:34 -0800[diff] [blame]38 spi: spi {
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]39 #address-cells = <1>;
40 #size-cells = <0>;
Bin Meng1f9eb592016-02-01 01:40:37 -0800[diff] [blame]41 compatible = "intel,ich9-spi";
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]42 spi-flash@0 {
43 reg = <0>;
44 compatible = "winbond,w25q128", "spi-flash";
45 memory-map = <0xff000000 0x01000000>;
46 };
47 };
George McCollistere0ae6482015-10-21 08:05:33 -0500[diff] [blame]48 };
49 };
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]50
George McCollistere0ae6482015-10-21 08:05:33 -0500[diff] [blame]51};