blob: 2f60911549425f4cc28747e7717eed89ef4040f3 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard4fadcaf2017-08-09 14:45:27 +02002/*
3 * (C) Copyright 2017 STMicroelectronics
Patrice Chotard4fadcaf2017-08-09 14:45:27 +02004 */
5
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
9#include <i2c.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +020011#include <regmap.h>
Patrice Chotard4fadcaf2017-08-09 14:45:27 +020012#include <reset.h>
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +020013#include <syscon.h>
Simon Glasscd93d622020-05-10 11:40:13 -060014#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060015#include <linux/delay.h>
Patrice Chotard4fadcaf2017-08-09 14:45:27 +020016
17#include <dm/device.h>
Alain Volmatc3244652020-03-06 11:09:14 +010018#include <linux/err.h>
Patrice Chotard4fadcaf2017-08-09 14:45:27 +020019#include <linux/io.h>
20
21/* STM32 I2C registers */
22struct stm32_i2c_regs {
23 u32 cr1; /* I2C control register 1 */
24 u32 cr2; /* I2C control register 2 */
25 u32 oar1; /* I2C own address 1 register */
26 u32 oar2; /* I2C own address 2 register */
27 u32 timingr; /* I2C timing register */
28 u32 timeoutr; /* I2C timeout register */
29 u32 isr; /* I2C interrupt and status register */
30 u32 icr; /* I2C interrupt clear register */
31 u32 pecr; /* I2C packet error checking register */
32 u32 rxdr; /* I2C receive data register */
33 u32 txdr; /* I2C transmit data register */
34};
35
36#define STM32_I2C_CR1 0x00
37#define STM32_I2C_CR2 0x04
38#define STM32_I2C_TIMINGR 0x10
39#define STM32_I2C_ISR 0x18
40#define STM32_I2C_ICR 0x1C
41#define STM32_I2C_RXDR 0x24
42#define STM32_I2C_TXDR 0x28
43
44/* STM32 I2C control 1 */
45#define STM32_I2C_CR1_ANFOFF BIT(12)
46#define STM32_I2C_CR1_ERRIE BIT(7)
47#define STM32_I2C_CR1_TCIE BIT(6)
48#define STM32_I2C_CR1_STOPIE BIT(5)
49#define STM32_I2C_CR1_NACKIE BIT(4)
50#define STM32_I2C_CR1_ADDRIE BIT(3)
51#define STM32_I2C_CR1_RXIE BIT(2)
52#define STM32_I2C_CR1_TXIE BIT(1)
53#define STM32_I2C_CR1_PE BIT(0)
54
55/* STM32 I2C control 2 */
56#define STM32_I2C_CR2_AUTOEND BIT(25)
57#define STM32_I2C_CR2_RELOAD BIT(24)
58#define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
59#define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
60#define STM32_I2C_CR2_NACK BIT(15)
61#define STM32_I2C_CR2_STOP BIT(14)
62#define STM32_I2C_CR2_START BIT(13)
63#define STM32_I2C_CR2_HEAD10R BIT(12)
64#define STM32_I2C_CR2_ADD10 BIT(11)
65#define STM32_I2C_CR2_RD_WRN BIT(10)
66#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
Patrick Delaunayc0765f42018-10-29 15:31:55 +010067#define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +020068#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
69#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
70#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
71 | STM32_I2C_CR2_NBYTES_MASK \
72 | STM32_I2C_CR2_SADD7_MASK \
73 | STM32_I2C_CR2_RELOAD \
74 | STM32_I2C_CR2_RD_WRN)
75
76/* STM32 I2C Interrupt Status */
77#define STM32_I2C_ISR_BUSY BIT(15)
78#define STM32_I2C_ISR_ARLO BIT(9)
79#define STM32_I2C_ISR_BERR BIT(8)
80#define STM32_I2C_ISR_TCR BIT(7)
81#define STM32_I2C_ISR_TC BIT(6)
82#define STM32_I2C_ISR_STOPF BIT(5)
83#define STM32_I2C_ISR_NACKF BIT(4)
84#define STM32_I2C_ISR_ADDR BIT(3)
85#define STM32_I2C_ISR_RXNE BIT(2)
86#define STM32_I2C_ISR_TXIS BIT(1)
87#define STM32_I2C_ISR_TXE BIT(0)
88#define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
89 | STM32_I2C_ISR_ARLO)
90
91/* STM32 I2C Interrupt Clear */
92#define STM32_I2C_ICR_ARLOCF BIT(9)
93#define STM32_I2C_ICR_BERRCF BIT(8)
94#define STM32_I2C_ICR_STOPCF BIT(5)
95#define STM32_I2C_ICR_NACKCF BIT(4)
96
97/* STM32 I2C Timing */
98#define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
99#define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
100#define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
101#define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
102#define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
103
104#define STM32_I2C_MAX_LEN 0xff
105
106#define STM32_I2C_DNF_DEFAULT 0
107#define STM32_I2C_DNF_MAX 16
108
109#define STM32_I2C_ANALOG_FILTER_ENABLE 1
110#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
111#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
112
113#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
114#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
115
116#define STM32_PRESC_MAX BIT(4)
117#define STM32_SCLDEL_MAX BIT(4)
118#define STM32_SDADEL_MAX BIT(4)
119#define STM32_SCLH_MAX BIT(8)
120#define STM32_SCLL_MAX BIT(8)
121
122#define STM32_NSEC_PER_SEC 1000000000L
123
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200124/**
125 * struct stm32_i2c_spec - private i2c specification timing
126 * @rate: I2C bus speed (Hz)
127 * @rate_min: 80% of I2C bus speed (Hz)
128 * @rate_max: 120% of I2C bus speed (Hz)
129 * @fall_max: Max fall time of both SDA and SCL signals (ns)
130 * @rise_max: Max rise time of both SDA and SCL signals (ns)
131 * @hddat_min: Min data hold time (ns)
132 * @vddat_max: Max data valid time (ns)
133 * @sudat_min: Min data setup time (ns)
134 * @l_min: Min low period of the SCL clock (ns)
135 * @h_min: Min high period of the SCL clock (ns)
136 */
137
138struct stm32_i2c_spec {
139 u32 rate;
140 u32 rate_min;
141 u32 rate_max;
142 u32 fall_max;
143 u32 rise_max;
144 u32 hddat_min;
145 u32 vddat_max;
146 u32 sudat_min;
147 u32 l_min;
148 u32 h_min;
149};
150
151/**
152 * struct stm32_i2c_setup - private I2C timing setup parameters
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200153 * @speed_freq: I2C speed frequency (Hz)
154 * @clock_src: I2C clock source frequency (Hz)
155 * @rise_time: Rise time (ns)
156 * @fall_time: Fall time (ns)
157 * @dnf: Digital filter coefficient (0-16)
158 * @analog_filter: Analog filter delay (On/Off)
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200159 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200160 */
161struct stm32_i2c_setup {
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200162 u32 speed_freq;
163 u32 clock_src;
164 u32 rise_time;
165 u32 fall_time;
166 u8 dnf;
167 bool analog_filter;
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200168 u32 fmp_clr_offset;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200169};
170
171/**
172 * struct stm32_i2c_timings - private I2C output parameters
173 * @prec: Prescaler value
174 * @scldel: Data setup time
175 * @sdadel: Data hold time
176 * @sclh: SCL high period (master mode)
177 * @sclh: SCL low period (master mode)
178 */
179struct stm32_i2c_timings {
180 struct list_head node;
181 u8 presc;
182 u8 scldel;
183 u8 sdadel;
184 u8 sclh;
185 u8 scll;
186};
187
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200188/**
189 * struct stm32_i2c_priv - private data of the controller
190 * @regs: I2C registers address
191 * @clk: hw i2c clock
192 * @setup: I2C timing setup parameters
193 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
194 * @regmap: holds SYSCFG phandle for Fast Mode Plus bit
195 * @regmap_sreg: register address for setting Fast Mode Plus bits
196 * @regmap_creg: register address for clearing Fast Mode Plus bits
197 * @regmap_mask: mask for Fast Mode Plus bits
198 */
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200199struct stm32_i2c_priv {
200 struct stm32_i2c_regs *regs;
201 struct clk clk;
202 struct stm32_i2c_setup *setup;
Alain Volmatc3244652020-03-06 11:09:14 +0100203 u32 speed;
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200204 struct regmap *regmap;
205 u32 regmap_sreg;
206 u32 regmap_creg;
207 u32 regmap_mask;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200208};
209
Patrick Delaunayc235b082018-10-29 15:31:56 +0100210static const struct stm32_i2c_spec i2c_specs[] = {
Alain Volmatc3244652020-03-06 11:09:14 +0100211 /* Standard speed - 100 KHz */
Simon Glassb0a22d02020-01-23 11:48:21 -0700212 [IC_SPEED_MODE_STANDARD] = {
213 .rate = I2C_SPEED_STANDARD_RATE,
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200214 .rate_min = 8000,
215 .rate_max = 120000,
216 .fall_max = 300,
217 .rise_max = 1000,
218 .hddat_min = 0,
219 .vddat_max = 3450,
220 .sudat_min = 250,
221 .l_min = 4700,
222 .h_min = 4000,
223 },
Alain Volmatc3244652020-03-06 11:09:14 +0100224 /* Fast speed - 400 KHz */
Simon Glassb0a22d02020-01-23 11:48:21 -0700225 [IC_SPEED_MODE_FAST] = {
226 .rate = I2C_SPEED_FAST_RATE,
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200227 .rate_min = 320000,
228 .rate_max = 480000,
229 .fall_max = 300,
230 .rise_max = 300,
231 .hddat_min = 0,
232 .vddat_max = 900,
233 .sudat_min = 100,
234 .l_min = 1300,
235 .h_min = 600,
236 },
Alain Volmatc3244652020-03-06 11:09:14 +0100237 /* Fast Plus Speed - 1 MHz */
Simon Glassb0a22d02020-01-23 11:48:21 -0700238 [IC_SPEED_MODE_FAST_PLUS] = {
239 .rate = I2C_SPEED_FAST_PLUS_RATE,
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200240 .rate_min = 800000,
241 .rate_max = 1200000,
242 .fall_max = 100,
243 .rise_max = 120,
244 .hddat_min = 0,
245 .vddat_max = 450,
246 .sudat_min = 50,
247 .l_min = 500,
248 .h_min = 260,
249 },
250};
251
Patrick Delaunayc235b082018-10-29 15:31:56 +0100252static const struct stm32_i2c_setup stm32f7_setup = {
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200253 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
254 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
255 .dnf = STM32_I2C_DNF_DEFAULT,
256 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
257};
258
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200259static const struct stm32_i2c_setup stm32mp15_setup = {
260 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
261 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
262 .dnf = STM32_I2C_DNF_DEFAULT,
263 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
264 .fmp_clr_offset = 0x40,
265};
266
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200267static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
268{
269 struct stm32_i2c_regs *regs = i2c_priv->regs;
270 u32 status = readl(&regs->isr);
271
272 if (status & STM32_I2C_ISR_BUSY)
273 return -EBUSY;
274
275 return 0;
276}
277
278static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100279 struct i2c_msg *msg, bool stop)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200280{
281 struct stm32_i2c_regs *regs = i2c_priv->regs;
282 u32 cr2 = readl(&regs->cr2);
283
284 /* Set transfer direction */
285 cr2 &= ~STM32_I2C_CR2_RD_WRN;
286 if (msg->flags & I2C_M_RD)
287 cr2 |= STM32_I2C_CR2_RD_WRN;
288
289 /* Set slave address */
290 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
291 if (msg->flags & I2C_M_TEN) {
292 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
293 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
294 cr2 |= STM32_I2C_CR2_ADD10;
295 } else {
296 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
297 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
298 }
299
300 /* Set nb bytes to transfer and reload or autoend bits */
301 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
302 STM32_I2C_CR2_AUTOEND);
303 if (msg->len > STM32_I2C_MAX_LEN) {
304 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
305 cr2 |= STM32_I2C_CR2_RELOAD;
306 } else {
307 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
308 }
309
310 /* Write configurations register */
311 writel(cr2, &regs->cr2);
312
313 /* START/ReSTART generation */
314 setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
315}
316
317/*
318 * RELOAD mode must be selected if total number of data bytes to be
319 * sent is greater than MAX_LEN
320 */
321
322static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100323 struct i2c_msg *msg, bool stop)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200324{
325 struct stm32_i2c_regs *regs = i2c_priv->regs;
326 u32 cr2 = readl(&regs->cr2);
327
328 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
329
330 if (msg->len > STM32_I2C_MAX_LEN) {
331 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
332 } else {
333 cr2 &= ~STM32_I2C_CR2_RELOAD;
334 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
335 }
336
337 writel(cr2, &regs->cr2);
338}
339
340static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100341 u32 flags, u32 *status)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200342{
343 struct stm32_i2c_regs *regs = i2c_priv->regs;
344 u32 time_start = get_timer(0);
345
346 *status = readl(&regs->isr);
347 while (!(*status & flags)) {
348 if (get_timer(time_start) > CONFIG_SYS_HZ) {
349 debug("%s: i2c timeout\n", __func__);
350 return -ETIMEDOUT;
351 }
352
353 *status = readl(&regs->isr);
354 }
355
356 return 0;
357}
358
359static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
360{
361 struct stm32_i2c_regs *regs = i2c_priv->regs;
362 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
363 STM32_I2C_ISR_STOPF;
364 u32 status;
365 int ret;
366
367 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
368 if (ret)
369 return ret;
370
371 if (status & STM32_I2C_ISR_BERR) {
372 debug("%s: Bus error\n", __func__);
373
374 /* Clear BERR flag */
375 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
376
377 return -EIO;
378 }
379
380 if (status & STM32_I2C_ISR_ARLO) {
381 debug("%s: Arbitration lost\n", __func__);
382
383 /* Clear ARLO flag */
384 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
385
386 return -EAGAIN;
387 }
388
389 if (status & STM32_I2C_ISR_NACKF) {
390 debug("%s: Receive NACK\n", __func__);
391
392 /* Clear NACK flag */
393 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
394
395 /* Wait until STOPF flag is set */
396 mask = STM32_I2C_ISR_STOPF;
397 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
398 if (ret)
399 return ret;
400
401 ret = -EIO;
402 }
403
404 if (status & STM32_I2C_ISR_STOPF) {
405 /* Clear STOP flag */
406 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
407
408 /* Clear control register 2 */
409 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
410 }
411
412 return ret;
413}
414
415static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100416 struct i2c_msg *msg, bool stop)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200417{
418 struct stm32_i2c_regs *regs = i2c_priv->regs;
419 u32 status;
420 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
421 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
422 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
423 STM32_I2C_MAX_LEN : msg->len;
424 int ret = 0;
425
426 /* Add errors */
427 mask |= STM32_I2C_ISR_ERRORS;
428
429 stm32_i2c_message_start(i2c_priv, msg, stop);
430
431 while (msg->len) {
432 /*
433 * Wait until TXIS/NACKF/BERR/ARLO flags or
434 * RXNE/BERR/ARLO flags are set
435 */
436 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
437 if (ret)
438 break;
439
440 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
441 break;
442
443 if (status & STM32_I2C_ISR_RXNE) {
444 *msg->buf++ = readb(&regs->rxdr);
445 msg->len--;
446 bytes_to_rw--;
447 }
448
449 if (status & STM32_I2C_ISR_TXIS) {
450 writeb(*msg->buf++, &regs->txdr);
451 msg->len--;
452 bytes_to_rw--;
453 }
454
455 if (!bytes_to_rw && msg->len) {
456 /* Wait until TCR flag is set */
457 mask = STM32_I2C_ISR_TCR;
458 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
459 if (ret)
460 break;
461
462 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
463 STM32_I2C_MAX_LEN : msg->len;
464 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
465 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
466
467 stm32_i2c_handle_reload(i2c_priv, msg, stop);
468 } else if (!bytes_to_rw) {
469 /* Wait until TC flag is set */
470 mask = STM32_I2C_ISR_TC;
471 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
472 if (ret)
473 break;
474
475 if (!stop)
476 /* Message sent, new message has to be sent */
477 return 0;
478 }
479 }
480
481 /* End of transfer, send stop condition */
482 mask = STM32_I2C_CR2_STOP;
483 setbits_le32(&regs->cr2, mask);
484
485 return stm32_i2c_check_end_of_message(i2c_priv);
486}
487
488static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100489 int nmsgs)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200490{
491 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
492 int ret;
493
494 ret = stm32_i2c_check_device_busy(i2c_priv);
495 if (ret)
496 return ret;
497
498 for (; nmsgs > 0; nmsgs--, msg++) {
499 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
500 if (ret)
501 return ret;
502 }
503
504 return 0;
505}
506
507static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
Alain Volmatc3244652020-03-06 11:09:14 +0100508 const struct stm32_i2c_spec *specs,
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200509 struct list_head *solutions)
510{
511 struct stm32_i2c_timings *v;
512 u32 p_prev = STM32_PRESC_MAX;
513 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
514 setup->clock_src);
515 u32 af_delay_min, af_delay_max;
516 u16 p, l, a;
517 int sdadel_min, sdadel_max, scldel_min;
518 int ret = 0;
519
520 af_delay_min = setup->analog_filter ?
521 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
522 af_delay_max = setup->analog_filter ?
523 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
524
Alain Volmatc3244652020-03-06 11:09:14 +0100525 sdadel_min = specs->hddat_min + setup->fall_time -
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200526 af_delay_min - (setup->dnf + 3) * i2cclk;
527
Alain Volmatc3244652020-03-06 11:09:14 +0100528 sdadel_max = specs->vddat_max - setup->rise_time -
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200529 af_delay_max - (setup->dnf + 4) * i2cclk;
530
Alain Volmatc3244652020-03-06 11:09:14 +0100531 scldel_min = setup->rise_time + specs->sudat_min;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200532
533 if (sdadel_min < 0)
534 sdadel_min = 0;
535 if (sdadel_max < 0)
536 sdadel_max = 0;
537
538 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
539 sdadel_min, sdadel_max, scldel_min);
540
541 /* Compute possible values for PRESC, SCLDEL and SDADEL */
542 for (p = 0; p < STM32_PRESC_MAX; p++) {
543 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
Patrick Delaunay499504b2019-06-21 15:26:47 +0200544 int scldel = (l + 1) * (p + 1) * i2cclk;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200545
546 if (scldel < scldel_min)
547 continue;
548
549 for (a = 0; a < STM32_SDADEL_MAX; a++) {
Patrick Delaunay499504b2019-06-21 15:26:47 +0200550 int sdadel = (a * (p + 1) + 1) * i2cclk;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200551
552 if (((sdadel >= sdadel_min) &&
553 (sdadel <= sdadel_max)) &&
554 (p != p_prev)) {
Patrick Delaunay35746c02018-03-12 10:46:09 +0100555 v = calloc(1, sizeof(*v));
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200556 if (!v)
557 return -ENOMEM;
558
559 v->presc = p;
560 v->scldel = l;
561 v->sdadel = a;
562 p_prev = p;
563
564 list_add_tail(&v->node, solutions);
Nicolas Le Bayon5237f372019-04-18 17:32:43 +0200565 break;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200566 }
567 }
Nicolas Le Bayon5237f372019-04-18 17:32:43 +0200568
569 if (p_prev == p)
570 break;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200571 }
572 }
573
574 if (list_empty(solutions)) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900575 pr_err("%s: no Prescaler solution\n", __func__);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200576 ret = -EPERM;
577 }
578
579 return ret;
580}
581
582static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
Alain Volmatc3244652020-03-06 11:09:14 +0100583 const struct stm32_i2c_spec *specs,
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200584 struct list_head *solutions,
585 struct stm32_i2c_timings *s)
586{
587 struct stm32_i2c_timings *v;
588 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
589 setup->speed_freq);
590 u32 clk_error_prev = i2cbus;
591 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
592 setup->clock_src);
593 u32 clk_min, clk_max;
594 u32 af_delay_min;
595 u32 dnf_delay;
596 u32 tsync;
597 u16 l, h;
Christophe Kerello81c48432017-10-17 11:21:32 +0200598 bool sol_found = false;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200599 int ret = 0;
600
601 af_delay_min = setup->analog_filter ?
602 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
603 dnf_delay = setup->dnf * i2cclk;
604
605 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
Alain Volmatc3244652020-03-06 11:09:14 +0100606 clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
607 clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200608
609 /*
610 * Among Prescaler possibilities discovered above figures out SCL Low
611 * and High Period. Provided:
612 * - SCL Low Period has to be higher than Low Period of the SCL Clock
613 * defined by I2C Specification. I2C Clock has to be lower than
614 * (SCL Low Period - Analog/Digital filters) / 4.
615 * - SCL High Period has to be lower than High Period of the SCL Clock
616 * defined by I2C Specification
617 * - I2C Clock has to be lower than SCL High Period
618 */
619 list_for_each_entry(v, solutions, node) {
620 u32 prescaler = (v->presc + 1) * i2cclk;
621
622 for (l = 0; l < STM32_SCLL_MAX; l++) {
623 u32 tscl_l = (l + 1) * prescaler + tsync;
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100624
Alain Volmatc3244652020-03-06 11:09:14 +0100625 if (tscl_l < specs->l_min ||
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200626 (i2cclk >=
627 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
628 continue;
629 }
630
631 for (h = 0; h < STM32_SCLH_MAX; h++) {
632 u32 tscl_h = (h + 1) * prescaler + tsync;
633 u32 tscl = tscl_l + tscl_h +
634 setup->rise_time + setup->fall_time;
635
636 if ((tscl >= clk_min) && (tscl <= clk_max) &&
Alain Volmatc3244652020-03-06 11:09:14 +0100637 (tscl_h >= specs->h_min) &&
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200638 (i2cclk < tscl_h)) {
Patrick Delaunay499504b2019-06-21 15:26:47 +0200639 u32 clk_error;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200640
Patrick Delaunay499504b2019-06-21 15:26:47 +0200641 if (tscl > i2cbus)
642 clk_error = tscl - i2cbus;
643 else
644 clk_error = i2cbus - tscl;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200645
646 if (clk_error < clk_error_prev) {
647 clk_error_prev = clk_error;
648 v->scll = l;
649 v->sclh = h;
Christophe Kerello81c48432017-10-17 11:21:32 +0200650 sol_found = true;
651 memcpy(s, v, sizeof(*s));
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200652 }
653 }
654 }
655 }
656 }
657
Christophe Kerello81c48432017-10-17 11:21:32 +0200658 if (!sol_found) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900659 pr_err("%s: no solution at all\n", __func__);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200660 ret = -EPERM;
661 }
662
663 return ret;
664}
665
Alain Volmatc3244652020-03-06 11:09:14 +0100666static const struct stm32_i2c_spec *get_specs(u32 rate)
667{
668 unsigned int i;
669
670 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
671 if (rate <= i2c_specs[i].rate)
672 return &i2c_specs[i];
673
674 /* NOT REACHED */
675 return ERR_PTR(-EINVAL);
676}
677
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200678static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100679 struct stm32_i2c_setup *setup,
680 struct stm32_i2c_timings *output)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200681{
Alain Volmatc3244652020-03-06 11:09:14 +0100682 const struct stm32_i2c_spec *specs;
Patrice Chotardd10bd6c2017-10-17 11:21:33 +0200683 struct stm32_i2c_timings *v, *_v;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200684 struct list_head solutions;
685 int ret;
686
Alain Volmatc3244652020-03-06 11:09:14 +0100687 specs = get_specs(setup->speed_freq);
688 if (specs == ERR_PTR(-EINVAL)) {
689 pr_err("%s: speed out of bound {%d}\n", __func__,
690 setup->speed_freq);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200691 return -EINVAL;
692 }
693
Alain Volmatc3244652020-03-06 11:09:14 +0100694 if (setup->rise_time > specs->rise_max ||
695 setup->fall_time > specs->fall_max) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900696 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100697 __func__,
Alain Volmatc3244652020-03-06 11:09:14 +0100698 setup->rise_time, specs->rise_max,
699 setup->fall_time, specs->fall_max);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200700 return -EINVAL;
701 }
702
703 if (setup->dnf > STM32_I2C_DNF_MAX) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900704 pr_err("%s: DNF out of bound %d/%d\n", __func__,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100705 setup->dnf, STM32_I2C_DNF_MAX);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200706 return -EINVAL;
707 }
708
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200709 INIT_LIST_HEAD(&solutions);
Alain Volmatc3244652020-03-06 11:09:14 +0100710 ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200711 if (ret)
712 goto exit;
713
Alain Volmatc3244652020-03-06 11:09:14 +0100714 ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200715 if (ret)
716 goto exit;
717
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200718 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
719 __func__, output->presc,
720 output->scldel, output->sdadel,
721 output->scll, output->sclh);
722
723exit:
724 /* Release list and memory */
725 list_for_each_entry_safe(v, _v, &solutions, node) {
726 list_del(&v->node);
Patrick Delaunay35746c02018-03-12 10:46:09 +0100727 free(v);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200728 }
729
730 return ret;
731}
732
Alain Volmatc3244652020-03-06 11:09:14 +0100733static u32 get_lower_rate(u32 rate)
734{
735 int i;
736
737 for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
738 if (rate > i2c_specs[i].rate)
739 return i2c_specs[i].rate;
740
741 return i2c_specs[0].rate;
742}
743
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200744static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
Patrick Delaunayc0765f42018-10-29 15:31:55 +0100745 struct stm32_i2c_timings *timing)
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200746{
747 struct stm32_i2c_setup *setup = i2c_priv->setup;
748 int ret = 0;
749
Alain Volmatc3244652020-03-06 11:09:14 +0100750 setup->speed_freq = i2c_priv->speed;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200751 setup->clock_src = clk_get_rate(&i2c_priv->clk);
752
753 if (!setup->clock_src) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900754 pr_err("%s: clock rate is 0\n", __func__);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200755 return -EINVAL;
756 }
757
758 do {
759 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
760 if (ret) {
761 debug("%s: failed to compute I2C timings.\n",
762 __func__);
Alain Volmatc3244652020-03-06 11:09:14 +0100763 if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200764 setup->speed_freq =
Alain Volmatc3244652020-03-06 11:09:14 +0100765 get_lower_rate(setup->speed_freq);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200766 debug("%s: downgrade I2C Speed Freq to (%i)\n",
Alain Volmatc3244652020-03-06 11:09:14 +0100767 __func__, setup->speed_freq);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200768 } else {
769 break;
770 }
771 }
772 } while (ret);
773
774 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900775 pr_err("%s: impossible to compute I2C timings.\n", __func__);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200776 return ret;
777 }
778
Alain Volmatc3244652020-03-06 11:09:14 +0100779 debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
780 setup->speed_freq, setup->clock_src);
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200781 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
782 setup->rise_time, setup->fall_time);
783 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
784 setup->analog_filter ? "On" : "Off", setup->dnf);
785
Alain Volmatc3244652020-03-06 11:09:14 +0100786 i2c_priv->speed = setup->speed_freq;
787
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200788 return 0;
789}
790
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200791static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv)
792{
793 int ret;
794 bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE;
795
796 /* Optional */
797 if (IS_ERR_OR_NULL(i2c_priv->regmap))
798 return 0;
799
800 if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg)
801 ret = regmap_update_bits(i2c_priv->regmap,
802 i2c_priv->regmap_sreg,
803 i2c_priv->regmap_mask,
804 enable ? i2c_priv->regmap_mask : 0);
805 else
806 ret = regmap_write(i2c_priv->regmap,
807 enable ? i2c_priv->regmap_sreg :
808 i2c_priv->regmap_creg,
809 i2c_priv->regmap_mask);
810
811 return ret;
812}
813
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200814static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
815{
816 struct stm32_i2c_regs *regs = i2c_priv->regs;
817 struct stm32_i2c_timings t;
818 int ret;
819 u32 timing = 0;
820
821 ret = stm32_i2c_setup_timing(i2c_priv, &t);
822 if (ret)
823 return ret;
824
825 /* Disable I2C */
826 clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
827
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200828 /* Setup Fast mode plus if necessary */
829 ret = stm32_i2c_write_fm_plus_bits(i2c_priv);
830 if (ret)
831 return ret;
832
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200833 /* Timing settings */
834 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
835 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
836 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
837 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
838 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
839 writel(timing, &regs->timingr);
840
841 /* Enable I2C */
842 if (i2c_priv->setup->analog_filter)
843 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
844 else
845 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
846 setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
847
848 return 0;
849}
850
851static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
852{
853 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
854
Alain Volmatc3244652020-03-06 11:09:14 +0100855 if (speed > I2C_SPEED_FAST_PLUS_RATE) {
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200856 debug("%s: Speed %d not supported\n", __func__, speed);
857 return -EINVAL;
858 }
859
Alain Volmatc3244652020-03-06 11:09:14 +0100860 i2c_priv->speed = speed;
861
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200862 return stm32_i2c_hw_config(i2c_priv);
863}
864
865static int stm32_i2c_probe(struct udevice *dev)
866{
867 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
868 struct reset_ctl reset_ctl;
869 fdt_addr_t addr;
870 int ret;
871
872 addr = dev_read_addr(dev);
873 if (addr == FDT_ADDR_T_NONE)
874 return -EINVAL;
875
876 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
877
878 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
879 if (ret)
880 return ret;
881
882 ret = clk_enable(&i2c_priv->clk);
883 if (ret)
884 goto clk_free;
885
886 ret = reset_get_by_index(dev, 0, &reset_ctl);
887 if (ret)
888 goto clk_disable;
889
890 reset_assert(&reset_ctl);
891 udelay(2);
892 reset_deassert(&reset_ctl);
893
894 return 0;
895
896clk_disable:
897 clk_disable(&i2c_priv->clk);
898clk_free:
899 clk_free(&i2c_priv->clk);
900
901 return ret;
902}
903
904static int stm32_ofdata_to_platdata(struct udevice *dev)
905{
906 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
907 u32 rise_time, fall_time;
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200908 int ret;
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200909
910 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
911 if (!i2c_priv->setup)
912 return -EINVAL;
913
914 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
915 if (rise_time)
916 i2c_priv->setup->rise_time = rise_time;
917
918 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
919 if (fall_time)
920 i2c_priv->setup->fall_time = fall_time;
921
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200922 /* Optional */
923 i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
924 "st,syscfg-fmp");
925 if (!IS_ERR(i2c_priv->regmap)) {
926 u32 fmp[3];
927
928 ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3);
929 if (ret)
930 return ret;
931
932 i2c_priv->regmap_sreg = fmp[1];
933 i2c_priv->regmap_creg = fmp[1] +
934 i2c_priv->setup->fmp_clr_offset;
935 i2c_priv->regmap_mask = fmp[2];
936 }
937
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200938 return 0;
939}
940
941static const struct dm_i2c_ops stm32_i2c_ops = {
942 .xfer = stm32_i2c_xfer,
943 .set_bus_speed = stm32_i2c_set_bus_speed,
944};
945
946static const struct udevice_id stm32_i2c_of_match[] = {
947 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
Patrick Delaunay7ce87dc2020-07-06 13:31:35 +0200948 { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup },
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200949 {}
950};
951
952U_BOOT_DRIVER(stm32f7_i2c) = {
953 .name = "stm32f7-i2c",
954 .id = UCLASS_I2C,
955 .of_match = stm32_i2c_of_match,
956 .ofdata_to_platdata = stm32_ofdata_to_platdata,
957 .probe = stm32_i2c_probe,
958 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
959 .ops = &stm32_i2c_ops,
960};