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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liu48c6f322014-11-24 17:11:56 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 *
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +08005 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
Shengzhou Liu48c6f322014-11-24 17:11:56 +08006 */
7
8#include <common.h>
9#include <command.h>
10#include <netdev.h>
11#include <asm/mmu.h>
12#include <asm/processor.h>
13#include <asm/immap_85xx.h>
14#include <asm/fsl_law.h>
15#include <asm/fsl_serdes.h>
16#include <asm/fsl_portals.h>
17#include <asm/fsl_liodn.h>
18#include <malloc.h>
19#include <fm_eth.h>
20#include <fsl_mdio.h>
21#include <miiphy.h>
22#include <phy.h>
Shaohui Xie8225b2f2015-10-26 19:47:47 +080023#include <fsl_dtsec.h>
Shengzhou Liu48c6f322014-11-24 17:11:56 +080024#include <asm/fsl_serdes.h>
Shengzhou Liue26416a2014-12-17 16:51:08 +080025#include "../common/fman.h"
Shengzhou Liu48c6f322014-11-24 17:11:56 +080026
27int board_eth_init(bd_t *bis)
28{
29#if defined(CONFIG_FMAN_ENET)
30 int i, interface;
31 struct memac_mdio_info dtsec_mdio_info;
32 struct memac_mdio_info tgec_mdio_info;
33 struct mii_dev *dev;
34 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
35 u32 srds_s1;
36
37 srds_s1 = in_be32(&gur->rcwsr[4]) &
38 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
39 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
40
41 dtsec_mdio_info.regs =
42 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
43
44 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
45
46 /* Register the 1G MDIO bus */
47 fm_memac_mdio_init(bis, &dtsec_mdio_info);
48
49 tgec_mdio_info.regs =
50 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
51 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
52
53 /* Register the 10G MDIO bus */
54 fm_memac_mdio_init(bis, &tgec_mdio_info);
55
Shengzhou Liue26416a2014-12-17 16:51:08 +080056 /* Set the on-board RGMII PHY address */
Shengzhou Liu48c6f322014-11-24 17:11:56 +080057 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
58
59 switch (srds_s1) {
York Sun960286b2016-12-28 08:43:34 -080060#ifdef CONFIG_TARGET_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +080061 case 0x95:
Shengzhou Liue26416a2014-12-17 16:51:08 +080062 /* set the on-board RGMII2 PHY */
63 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
64
65 /* set 10G XFI with Aquantia AQR105 PHY */
Shengzhou Liu48c6f322014-11-24 17:11:56 +080066 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
67 break;
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080068#endif
69 case 0x6a:
70 case 0x6b:
Shengzhou Liue26416a2014-12-17 16:51:08 +080071 case 0x77:
72 case 0x135:
73 /* set the on-board 2.5G SGMII AQR105 PHY */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080074 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
York Sun90824052016-12-28 08:43:33 -080075#ifdef CONFIG_TARGET_T1023RDB
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080076 /* set the on-board 1G SGMII RTL8211F PHY */
77 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
78#endif
Shengzhou Liue26416a2014-12-17 16:51:08 +080079 break;
Shengzhou Liu48c6f322014-11-24 17:11:56 +080080 default:
81 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
82 srds_s1);
83 break;
84 }
85
86 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
87 interface = fm_info_get_enet_if(i);
88 switch (interface) {
89 case PHY_INTERFACE_MODE_RGMII:
90 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
91 fm_info_set_mdio(i, dev);
92 break;
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080093 case PHY_INTERFACE_MODE_SGMII:
York Sun90824052016-12-28 08:43:33 -080094#if defined(CONFIG_TARGET_T1023RDB)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080095 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
York Sun960286b2016-12-28 08:43:34 -080096#elif defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080097 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
98#endif
99 fm_info_set_mdio(i, dev);
100 break;
Shengzhou Liue26416a2014-12-17 16:51:08 +0800101 case PHY_INTERFACE_MODE_SGMII_2500:
102 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
103 fm_info_set_mdio(i, dev);
104 break;
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800105 default:
106 break;
107 }
108 }
109
110 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
111 switch (fm_info_get_enet_if(i)) {
112 case PHY_INTERFACE_MODE_XGMII:
113 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
114 fm_info_set_mdio(i, dev);
115 break;
116 default:
117 break;
118 }
119 }
120
121 cpu_eth_init(bis);
122#endif /* CONFIG_FMAN_ENET */
123
124 return pci_eth_init(bis);
125}
126
Shengzhou Liue26416a2014-12-17 16:51:08 +0800127void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
128 enum fm_port port, int offset)
129{
York Sun960286b2016-12-28 08:43:34 -0800130#if defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800131 if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
132 (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
133 (port == FM1_DTSEC3)) {
Shengzhou Liue26416a2014-12-17 16:51:08 +0800134 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
Shengzhou Liuea753262015-04-14 17:56:50 +0800135 fdt_setprop_string(fdt, offset, "phy-connection-type",
136 "sgmii-2500");
Shengzhou Liue26416a2014-12-17 16:51:08 +0800137 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
138 }
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800139#endif
Shengzhou Liue26416a2014-12-17 16:51:08 +0800140}
141
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800142void fdt_fixup_board_enet(void *fdt)
143{
144}