blob: 438a189702d420375d18bd8ac954956e7e5393ea [file] [log] [blame]
Michael Walle4ceb5c62020-10-15 23:08:57 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __SL28_H
4#define __SL28_H
5
6#include <asm/arch/stream_id_lsch3.h>
7#include <asm/arch/config.h>
8#include <asm/arch/soc.h>
9
10/* we don't use hwconfig but this has to be defined.. */
11#define HWCONFIG_BUFFER_SIZE 256
12
13/* we don't have secure memory unless we have a BL31 */
14#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
15#undef CONFIG_SYS_MEM_RESERVE_SECURE
16#endif
17
18/* DDR */
Michael Walle4ceb5c62020-10-15 23:08:57 +020019#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
20
21#define CONFIG_VERY_BIG_RAM
22#define CONFIG_CHIP_SELECTS_PER_CTRL 4
23#define CONFIG_DIMM_SLOTS_PER_CTLR 1
24#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
26#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
28#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
29
30/* early stack pointer */
31#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0)
32
33/* memtest command */
34#define CONFIG_SYS_MEMTEST_START 0x80000000
35#define CONFIG_SYS_MEMTEST_END 0x9fffffff
36
37/* SMP */
38#define CPU_RELEASE_ADDR secondary_boot_addr
39
40/* generic timer */
41#define COUNTER_FREQUENCY 25000000
42
Michael Walle4ceb5c62020-10-15 23:08:57 +020043/* early heap for SPL DM */
44#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
45
46/* serial port */
Michael Walle4ceb5c62020-10-15 23:08:57 +020047#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
49
50#define CONFIG_SYS_CLK_FREQ 100000000
Michael Walle4ceb5c62020-10-15 23:08:57 +020051#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
52
Michael Walle4ceb5c62020-10-15 23:08:57 +020053/* ethernet */
54#define CONFIG_SYS_RX_ETH_BUFFER 8
55
56/* SPL */
57#define CONFIG_SPL_BSS_START_ADDR 0x80100000
58#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
59#define CONFIG_SPL_MAX_SIZE 0x20000
60#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
61
62#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
63#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
64#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
65
66/* environment */
67/* see include/configs/ti_armv7_common.h */
Michael Walle4ceb5c62020-10-15 23:08:57 +020068#define ENV_MEM_LAYOUT_SETTINGS \
69 "loadaddr=0x82000000\0" \
70 "kernel_addr_r=0x82000000\0" \
71 "fdt_addr_r=0x88000000\0" \
72 "bootm_size=0x10000000\0" \
73 "pxefile_addr_r=0x80100000\0" \
74 "scriptaddr=0x80000000\0" \
75 "ramdisk_addr_r=0x88080000\0"
76
77#define BOOT_TARGET_DEVICES(func) \
Michael Walle4ceb5c62020-10-15 23:08:57 +020078 func(MMC, mmc, 0) \
Michael Wallee668bec2020-12-20 22:35:13 +010079 func(MMC, mmc, 1) \
Michael Walle4ceb5c62020-10-15 23:08:57 +020080 func(NVME, nvme, 0) \
81 func(USB, usb, 0) \
Michael Walle805b2422021-01-08 00:08:59 +010082 func(SCSI, scsi, 0) \
Michael Walle4ceb5c62020-10-15 23:08:57 +020083 func(DHCP, dhcp, 0) \
84 func(PXE, pxe, 0)
85#include <config_distro_bootcmd.h>
86
87#define CONFIG_EXTRA_ENV_SETTINGS \
88 "env_addr=0x203e0004\0" \
89 "envload=env import -d -b ${env_addr}\0" \
90 "install_rcw=source 20200000\0" \
91 "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \
92 ENV_MEM_LAYOUT_SETTINGS \
93 BOOTENV
94
95#endif /* __SL28_H */