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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf12e5682003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
21#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenkf12e5682003-07-07 20:07:54 +000025#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020026#define CONFIG_SYS_SMC_RXBUFLEN 128
27#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000028#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf12e5682003-07-07 20:07:54 +000029
wdenkae3af052003-08-07 22:18:11 +000030#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000031
Wolfgang Denke7e00102011-11-04 15:55:51 +000032#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
33
wdenkf12e5682003-07-07 20:07:54 +000034#define CONFIG_BOARD_TYPES 1 /* support board types */
35
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010036#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf12e5682003-07-07 20:07:54 +000037
38#undef CONFIG_BOOTARGS
39
40#define CONFIG_EXTRA_ENV_SETTINGS \
41 "netdev=eth0\0" \
42 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010043 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000044 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010045 "addip=setenv bootargs ${bootargs} " \
46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
47 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000048 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010049 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000050 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
52 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000053 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020054 "hostname=TQM850M\0" \
55 "bootfile=TQM850M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020056 "fdt_addr=40080000\0" \
57 "kernel_addr=400A0000\0" \
58 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020059 "u-boot=TQM850M/u-image.bin\0" \
60 "load=tftp 200000 ${u-boot}\0" \
61 "update=prot off 40000000 +${filesize};" \
62 "era 40000000 +${filesize};" \
63 "cp.b 200000 40000000 ${filesize};" \
64 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000065 ""
66#define CONFIG_BOOTCOMMAND "run flash_self"
67
68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000070
71#undef CONFIG_WATCHDOG /* watchdog disabled */
72
73#define CONFIG_STATUS_LED 1 /* Status LED enabled */
74
75#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
76
Jon Loeliger37d4bb72007-07-09 21:38:02 -050077/*
78 * BOOTP options
79 */
80#define CONFIG_BOOTP_SUBNETMASK
81#define CONFIG_BOOTP_GATEWAY
82#define CONFIG_BOOTP_HOSTNAME
83#define CONFIG_BOOTP_BOOTPATH
84#define CONFIG_BOOTP_BOOTFILESIZE
85
wdenkf12e5682003-07-07 20:07:54 +000086
87#define CONFIG_MAC_PARTITION
88#define CONFIG_DOS_PARTITION
89
90#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
91
Jon Loeliger26946902007-07-04 22:30:50 -050092/*
93 * Command line configuration.
94 */
95#include <config_cmd_default.h>
wdenkf12e5682003-07-07 20:07:54 +000096
Jon Loeliger26946902007-07-04 22:30:50 -050097#define CONFIG_CMD_ASKENV
98#define CONFIG_CMD_DATE
99#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200100#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100101#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500102#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200103#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500104#define CONFIG_CMD_NFS
105#define CONFIG_CMD_SNTP
106
wdenkf12e5682003-07-07 20:07:54 +0000107
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200108#define CONFIG_NETCONSOLE
109
110
wdenkf12e5682003-07-07 20:07:54 +0000111/*
112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf12e5682003-07-07 20:07:54 +0000115
Wolfgang Denk2751a952006-10-28 02:29:14 +0200116#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000118
Jon Loeliger26946902007-07-04 22:30:50 -0500119#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000123#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000132
wdenkf12e5682003-07-07 20:07:54 +0000133/*
134 * Low Level Configuration Settings
135 * (address mappings, register initial values, etc.)
136 * You should know what you are doing if you make changes here.
137 */
138/*-----------------------------------------------------------------------
139 * Internal Memory Mapped Register
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000142
143/*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area (in DPRAM)
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200147#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200148#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000150
151/*-----------------------------------------------------------------------
152 * Start addresses for the final memory configuration
153 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_SDRAM_BASE 0x00000000
157#define CONFIG_SYS_FLASH_BASE 0x40000000
158#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
160#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000161
162/*
163 * For booting Linux, the board info and command line data
164 * have to be in the first 8 MB of memory, since this is
165 * the maximum mapped by the Linux kernel during initialization.
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000168
169/*-----------------------------------------------------------------------
170 * FLASH organization
171 */
wdenkf12e5682003-07-07 20:07:54 +0000172
Martin Krausee318d9e2007-09-27 11:10:08 +0200173/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200175#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
177#define CONFIG_SYS_FLASH_EMPTY_INFO
178#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
179#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
180#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000181
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200182#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200183#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
184#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
185#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000186
187/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200188#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200192
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200193#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
194
wdenkf12e5682003-07-07 20:07:54 +0000195/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200196 * Dynamic MTD partition support
197 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100198#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200199#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
200#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200201#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
202
203#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
204 "128k(dtb)," \
205 "1920k(kernel)," \
206 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200207 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200208
209/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000210 * Hardware Information Block
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
213#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
214#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000215
216/*-----------------------------------------------------------------------
217 * Cache Configuration
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500220#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000222#endif
223
224/*-----------------------------------------------------------------------
225 * SYPCR - System Protection Control 11-9
226 * SYPCR can only be written once after reset!
227 *-----------------------------------------------------------------------
228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
229 */
230#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
233#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000235#endif
236
237/*-----------------------------------------------------------------------
238 * SIUMCR - SIU Module Configuration 11-6
239 *-----------------------------------------------------------------------
240 * PCMCIA config., multi-function pin tri-state
241 */
242#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000244#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000246#endif /* CONFIG_CAN_DRIVER */
247
248/*-----------------------------------------------------------------------
249 * TBSCR - Time Base Status and Control 11-26
250 *-----------------------------------------------------------------------
251 * Clear Reference Interrupt Status, Timebase freezing enabled
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000254
255/*-----------------------------------------------------------------------
256 * RTCSC - Real-Time Clock Status and Control Register 11-27
257 *-----------------------------------------------------------------------
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000260
261/*-----------------------------------------------------------------------
262 * PISCR - Periodic Interrupt Status and Control 11-31
263 *-----------------------------------------------------------------------
264 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000267
268/*-----------------------------------------------------------------------
269 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
270 *-----------------------------------------------------------------------
271 * Reset PLL lock status sticky bit, timer expired status bit and timer
272 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000275
276/*-----------------------------------------------------------------------
277 * SCCR - System Clock and reset Control Register 15-27
278 *-----------------------------------------------------------------------
279 * Set clock output, timebase and RTC source and divider,
280 * power management and some other internal clocks
281 */
282#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000284 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
285 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000286
287/*-----------------------------------------------------------------------
288 * PCMCIA stuff
289 *-----------------------------------------------------------------------
290 *
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
293#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
294#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
295#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
296#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
297#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
298#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
299#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000300
301/*-----------------------------------------------------------------------
302 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
303 *-----------------------------------------------------------------------
304 */
305
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000306#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf12e5682003-07-07 20:07:54 +0000307#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
308
309#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
310#undef CONFIG_IDE_LED /* LED for ide not supported */
311#undef CONFIG_IDE_RESET /* reset for ide not supported */
312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
314#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000319
320/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000322
323/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000325
326/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000328
329/*-----------------------------------------------------------------------
330 *
331 *-----------------------------------------------------------------------
332 *
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000335
336/*
337 * Init Memory Controller:
338 *
339 * BR0/1 and OR0/1 (FLASH)
340 */
341
342#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
343#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
344
345/* used to re-map FLASH both when starting from SRAM or FLASH:
346 * restrict access enough to keep SRAM working (if any)
347 * but not too much to meddle with FLASH accesses
348 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
350#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000351
352/*
353 * FLASH timing:
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000356 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
359#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
360#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
363#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
364#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000365
366/*
367 * BR2/3 and OR2/3 (SDRAM)
368 *
369 */
370#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
371#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
372#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
373
374/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
378#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000379
380#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
382#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000383#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
385#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
386#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
387#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000388 BR_PS_8 | BR_MS_UPMB | BR_V )
389#endif /* CONFIG_CAN_DRIVER */
390
391/*
392 * Memory Periodic Timer Prescaler
393 *
394 * The Divider for PTA (refresh timer) configuration is based on an
395 * example SDRAM configuration (64 MBit, one bank). The adjustment to
396 * the number of chip selects (NCS) and the actually needed refresh
397 * rate is done by setting MPTPR.
398 *
399 * PTA is calculated from
400 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
401 *
402 * gclk CPU clock (not bus clock!)
403 * Trefresh Refresh cycle * 4 (four word bursts used)
404 *
405 * 4096 Rows from SDRAM example configuration
406 * 1000 factor s -> ms
407 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
408 * 4 Number of refresh cycles per period
409 * 64 Refresh cycle in ms per number of rows
410 * --------------------------------------------
411 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
412 *
413 * 50 MHz => 50.000.000 / Divider = 98
414 * 66 Mhz => 66.000.000 / Divider = 129
415 * 80 Mhz => 80.000.000 / Divider = 156
416 */
wdenke9132ea2004-04-24 23:23:30 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
419#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000420
421/*
422 * For 16 MBit, refresh rates could be 31.3 us
423 * (= 64 ms / 2K = 125 / quad bursts).
424 * For a simpler initialization, 15.6 us is used instead.
425 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
427 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000428 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
430#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000431
432/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
434#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000435
436/*
437 * MAMR settings for SDRAM
438 */
439
440/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000442 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
443 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
444/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000446 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
447 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
448
Heiko Schocher7026ead2010-02-09 15:50:27 +0100449/* pass open firmware flat tree */
450#define CONFIG_OF_LIBFDT 1
451#define CONFIG_OF_BOARD_SETUP 1
452#define CONFIG_HWCONFIG 1
453
wdenkf12e5682003-07-07 20:07:54 +0000454#endif /* __CONFIG_H */