blob: c22d6d0c758fd1ae6fe200943c0784777b0f3776 [file] [log] [blame]
Alexey Brodkina7069dd2014-02-04 12:56:19 +04001/*
2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_AXS101_H_
8#define _CONFIG_AXS101_H_
9
10/*
11 * CPU configuration
12 */
13#define CONFIG_ARC700
14#define CONFIG_ARC_MMU_VER 3
15#define CONFIG_SYS_CACHELINE_SIZE 32
16#define CONFIG_SYS_CLK_FREQ 750000000
17#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
18
Alexey Brodkin0cdd7622014-03-27 19:30:18 +040019/* NAND controller DMA doesn't work correctly with D$ enabled */
Alexey Brodkina7069dd2014-02-04 12:56:19 +040020#define CONFIG_SYS_DCACHE_OFF
21
22/*
23 * Board configuration
24 */
25#define CONFIG_SYS_GENERIC_BOARD
26#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
27
28#define CONFIG_ARCH_EARLY_INIT_R
29
30#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
31#define ARC_APB_PERIPHERAL_BASE 0xF0000000
32#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
33#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
34
35/*
36 * Memory configuration
37 */
38#define CONFIG_SYS_TEXT_BASE 0x81000000
39#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
40
41#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
42#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Alexey Brodkin0cdd7622014-03-27 19:30:18 +040043#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */
Alexey Brodkina7069dd2014-02-04 12:56:19 +040044
45#define CONFIG_SYS_INIT_SP_ADDR \
46 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
47
48#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
49#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
50#define CONFIG_SYS_LOAD_ADDR 0x82000000
51
52/*
53 * NAND Flash configuration
54 */
55#define CONFIG_SYS_NO_FLASH
56#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
57#define CONFIG_SYS_MAX_NAND_DEVICE 1
58
59/*
60 * UART configuration
61 *
62 * CONFIG_CONS_INDEX = 1 - Debug UART
63 * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
64 */
65#define CONFIG_CONS_INDEX 4
66#define CONFIG_SYS_NS16550
67#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE -4
69#if (CONFIG_CONS_INDEX == 1)
70 /* Debug UART */
71# define CONFIG_SYS_NS16550_CLK 33333000
72#else
73 /* FPGA UARTs use different clock */
74# define CONFIG_SYS_NS16550_CLK 33333333
75#endif
76#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
77#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
78#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
79#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
80#define CONFIG_SYS_NS16550_MEM32
81
82#define CONFIG_BAUDRATE 115200
83/*
84 * I2C configuration
85 */
86#define CONFIG_HARD_I2C
87#define CONFIG_DW_I2C
88#define CONFIG_I2C_MULTI_BUS
89#define CONFIG_I2C_ENV_EEPROM_BUS 2
90#define CONFIG_SYS_I2C_SPEED 100000
91#define CONFIG_SYS_I2C_SLAVE 0
92#define CONFIG_SYS_I2C_BASE 0xE001D000
93#define CONFIG_SYS_I2C_BASE1 0xE001E000
94#define CONFIG_SYS_I2C_BASE2 0xE001F000
95#define CONFIG_SYS_I2C_BUS_MAX 3
96#define IC_CLK 50
97
98/*
99 * EEPROM configuration
100 */
101#define CONFIG_SYS_I2C_MULTI_EEPROMS
102#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
103#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
104#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
105#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
Alexey Brodkin6bfa4422014-03-24 17:15:50 +0400106#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64
Alexey Brodkina7069dd2014-02-04 12:56:19 +0400107
108/*
109 * SD/MMC configuration
110 */
111#define CONFIG_MMC
112#define CONFIG_GENERIC_MMC
113#define CONFIG_DWMMC
114#define CONFIG_DOS_PARTITION
115
116/*
117 * Ethernet PHY configuration
118 */
119#define CONFIG_PHYLIB
120#define CONFIG_MII
121#define CONFIG_PHY_GIGE
122
123/*
124 * Ethernet configuration
125 */
126#define CONFIG_DESIGNWARE_ETH
127#define CONFIG_DW_AUTONEG
128#define CONFIG_DW_SEARCH_PHY
129#define CONFIG_NET_MULTI
130
131/*
132 * Command line configuration
133 */
134#include <config_cmd_default.h>
135
136#define CONFIG_CMD_DHCP
137#define CONFIG_CMD_EEPROM
138#define CONFIG_CMD_ELF
139#define CONFIG_CMD_FAT
140#define CONFIG_CMD_I2C
141#define CONFIG_CMD_MMC
142#define CONFIG_CMD_NAND
143#define CONFIG_CMD_PING
144#define CONFIG_CMD_RARP
145
146#define CONFIG_OF_LIBFDT
147
148#define CONFIG_AUTO_COMPLETE
149#define CONFIG_SYS_MAXARGS 16
150
151/*
152 * Environment settings
153 */
154#define CONFIG_ENV_IS_IN_EEPROM
155#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
156#define CONFIG_ENV_OFFSET 0
157
158/*
159 * Environment configuration
160 */
161#define CONFIG_BOOTDELAY 3
162#define CONFIG_BOOTFILE "uImage"
163#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
164#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
165
166/*
167 * Console configuration
168 */
169#define CONFIG_SYS_LONGHELP
Alexey Brodkinc42eb7f2014-02-08 10:30:59 +0400170#define CONFIG_SYS_PROMPT "AXS# "
Alexey Brodkina7069dd2014-02-04 12:56:19 +0400171#define CONFIG_SYS_CBSIZE 256
172#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
173#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
174 sizeof(CONFIG_SYS_PROMPT) + 16)
175
176/*
177 * Misc utility configuration
178 */
179#define CONFIG_BOUNCE_BUFFER
180
181#endif /* _CONFIG_AXS101_H_ */