blob: a0f9d293caa733c44e9082d058a73ebb01edebc7 [file] [log] [blame]
Valentin Longchamp877bfe32013-10-18 11:47:24 +02001/*
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _CONFIG_KMP204X_H
9#define _CONFIG_KMP204X_H
10
11#define CONFIG_PHYS_64BIT
12#define CONFIG_PPC_P2041
13
14#define CONFIG_SYS_TEXT_BASE 0xfff80000
15
16#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
17
Valentin Longchampcf7707a2014-01-27 11:49:10 +010018/* an additionnal option is required for UBI as subpage access is
19 * supported in u-boot */
20#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
21
Valentin Longchamp877bfe32013-10-18 11:47:24 +020022#define CONFIG_NAND_ECC_BCH
23
24/* common KM defines */
25#include "keymile-common.h"
26
27#define CONFIG_SYS_RAMBOOT
28#define CONFIG_RAMBOOT_PBL
29#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
30#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090031#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
32#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
Valentin Longchamp877bfe32013-10-18 11:47:24 +020033
34/* High Level Configuration Options */
35#define CONFIG_BOOKE
36#define CONFIG_E500 /* BOOKE e500 family */
37#define CONFIG_E500MC /* BOOKE e500mc family */
38#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Valentin Longchamp877bfe32013-10-18 11:47:24 +020039#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
40#define CONFIG_MP /* support multiple processors */
41
42#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
43#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
44#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
45#define CONFIG_PCI /* Enable PCI/PCIE */
46#define CONFIG_PCIE1 /* PCIE controler 1 */
47#define CONFIG_PCIE3 /* PCIE controler 3 */
48#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
49#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
50
51#define CONFIG_SYS_DPAA_RMAN /* RMan */
52
53#define CONFIG_FSL_LAW /* Use common FSL init code */
54
55/* Environment in SPI Flash */
56#define CONFIG_SYS_EXTRA_ENV_RELOC
57#define CONFIG_ENV_IS_IN_SPI_FLASH
58#define CONFIG_ENV_SPI_BUS 0
59#define CONFIG_ENV_SPI_CS 0
60#define CONFIG_ENV_SPI_MAX_HZ 20000000
61#define CONFIG_ENV_SPI_MODE 0
62#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
63#define CONFIG_ENV_SIZE 0x004000 /* 16K env */
64#define CONFIG_ENV_SECT_SIZE 0x010000
65#define CONFIG_ENV_OFFSET_REDUND 0x110000
66#define CONFIG_ENV_TOTAL_SIZE 0x020000
67
68#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
69
70#ifndef __ASSEMBLY__
71unsigned long get_board_sys_clk(unsigned long dummy);
72#endif
73#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
74
75/*
76 * These can be toggled for performance analysis, otherwise use default.
77 */
78#define CONFIG_SYS_CACHE_STASHING
79#define CONFIG_BACKSIDE_L2_CACHE
80#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
81#define CONFIG_BTB /* toggle branch predition */
82
83#define CONFIG_ENABLE_36BIT_PHYS
84
85#define CONFIG_ADDR_MAP
86#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
87
Valentin Longchamp18794942014-04-30 15:01:44 +020088#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
Valentin Longchamp877bfe32013-10-18 11:47:24 +020089
90/*
91 * Config the L3 Cache as L3 SRAM
92 */
93#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
94#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
95 CONFIG_RAMBOOT_TEXT_BASE)
96#define CONFIG_SYS_L3_SIZE (1024 << 10)
97#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
98
99#define CONFIG_SYS_DCSRBAR 0xf0000000
100#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
101
102/*
103 * DDR Setup
104 */
105#define CONFIG_VERY_BIG_RAM
106#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
107#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108
109#define CONFIG_DIMM_SLOTS_PER_CTLR 1
110#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
111
112#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -0700113#define CONFIG_SYS_FSL_DDR3
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200114#define CONFIG_FSL_DDR_INTERACTIVE
115
116#define CONFIG_SYS_SPD_BUS_NUM 0
117#define SPD_EEPROM_ADDRESS 0x54
118#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
119
120#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
122
123/******************************************************************************
124 * (PRAM usage)
125 * ... -------------------------------------------------------
126 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
127 * ... |<------------------- pram -------------------------->|
128 * ... -------------------------------------------------------
129 * @END_OF_RAM:
130 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
131 * @CONFIG_KM_PHRAM: address for /var
132 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
133 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
134 */
135
136/* size of rootfs in RAM */
137#define CONFIG_KM_ROOTFSSIZE 0x0
138/* pseudo-non volatile RAM [hex] */
139#define CONFIG_KM_PNVRAM 0x80000
140/* physical RAM MTD size [hex] */
141#define CONFIG_KM_PHRAM 0x100000
Valentin Longchamp848b31a2014-04-30 15:01:45 +0200142/* reserved pram area at the end of memory [hex]
143 * u-boot reserves some memory for the MP boot page */
144#define CONFIG_KM_RESERVED_PRAM 0x1000
145/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
146 * is not valid yet, which is the case for when u-boot copies itself to RAM */
147#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200148
149#define CONFIG_KM_CRAMFS_ADDR 0x2000000
150#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
151#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
152
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200153/*
154 * Local Bus Definitions
155 */
156
157/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
158#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
159
160/* Nand Flash */
161#define CONFIG_NAND_FSL_ELBC
162#define CONFIG_SYS_NAND_BASE 0xffa00000
163#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
164
165#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
166#define CONFIG_SYS_MAX_NAND_DEVICE 1
167#define CONFIG_MTD_NAND_VERIFY_WRITE
168#define CONFIG_CMD_NAND
169#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
170
171#define CONFIG_BCH
172
173/* NAND flash config */
174#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
175 | BR_PS_8 /* Port Size = 8 bit */ \
176 | BR_MS_FCM /* MSEL = FCM */ \
177 | BR_V) /* valid */
178
179#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
180 | OR_FCM_BCTLD /* LBCTL not ass */ \
181 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
182 | OR_FCM_RST /* 1 clk read setup */ \
183 | OR_FCM_PGS /* Large page size */ \
184 | OR_FCM_CST) /* 0.25 command setup */
185
186#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
187#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
188
189/* QRIO FPGA */
190#define CONFIG_SYS_QRIO_BASE 0xfb000000
191#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
192
193#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
194 | BR_PS_8 /* Port Size 8 bits */ \
195 | BR_DECC_OFF /* no error corr */ \
196 | BR_MS_GPCM /* MSEL = GPCM */ \
197 | BR_V) /* valid */
198
199#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
200 | OR_GPCM_BCTLD /* no LCTL assert */ \
201 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
202 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
203 | OR_GPCM_TRLX /* relaxed tmgs */ \
204 | OR_GPCM_EAD) /* extra bus clk cycles */
205
206#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
207#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
208
Rainer Boschungdd21f092014-01-27 11:49:04 +0100209/* bootcounter in QRIO */
210#define CONFIG_BOOTCOUNT_LIMIT
211#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
212
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200213#define CONFIG_BOARD_EARLY_INIT_F
214#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
Rainer Boschungf3e74d02014-02-03 08:45:40 +0100215#define CONFIG_MISC_INIT_F
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200216#define CONFIG_MISC_INIT_R
217#define CONFIG_LAST_STAGE_INIT
218
219#define CONFIG_HWCONFIG
220
221/* define to use L1 as initial stack */
222#define CONFIG_L1_INIT_RAM
223#define CONFIG_SYS_INIT_RAM_LOCK
224#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
225#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
226#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
227/* The assembler doesn't like typecast */
228#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
229 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
230 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
231#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
232
233#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
234 GENERATED_GBL_DATA_SIZE)
235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
236
237#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
238#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
239#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
240
241/* Serial Port - controlled on board with jumper J8
242 * open - index 2
243 * shorted - index 1
244 */
245#define CONFIG_CONS_INDEX 1
246#define CONFIG_SYS_NS16550
247#define CONFIG_SYS_NS16550_SERIAL
248#define CONFIG_SYS_NS16550_REG_SIZE 1
249#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
250
251#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
252#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
253#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
254#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
255
256#define CONFIG_KM_CONSOLE_TTY "ttyS0"
257
258/* Use the HUSH parser */
259#define CONFIG_SYS_HUSH_PARSER
260
261/* pass open firmware flat tree */
262#define CONFIG_OF_LIBFDT
263#define CONFIG_OF_BOARD_SETUP
264#define CONFIG_OF_STDOUT_VIA_ALIAS
265
266/* new uImage format support */
267#define CONFIG_FIT
268#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
269
270/* I2C */
Rainer Boschungf3e74d02014-02-03 08:45:40 +0100271
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200272#define CONFIG_SYS_I2C
Rainer Boschungf3e74d02014-02-03 08:45:40 +0100273#define CONFIG_SYS_I2C_INIT_BOARD
274#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200275#define CONFIG_SYS_NUM_I2C_BUSES 3
276#define CONFIG_SYS_I2C_MAX_HOPS 1
277#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
278#define CONFIG_I2C_MULTI_BUS
279#define CONFIG_I2C_CMD_TREE
280#define CONFIG_SYS_FSL_I2C_SPEED 400000
281#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
282#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
283#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
284 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
285 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
286 }
Rainer Boschungf3e74d02014-02-03 08:45:40 +0100287#ifndef __ASSEMBLY__
288void set_sda(int state);
289void set_scl(int state);
290int get_sda(void);
291int get_scl(void);
292#endif
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200293
294#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
295
296/*
297 * eSPI - Enhanced SPI
298 */
299#define CONFIG_FSL_ESPI
300#define CONFIG_SPI_FLASH
301#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
302#define CONFIG_SPI_FLASH_STMICRO
Valentin Longchamp47c11802014-01-27 11:49:11 +0100303#define CONFIG_SPI_FLASH_SPANSION
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200304#define CONFIG_CMD_SF
305#define CONFIG_SF_DEFAULT_SPEED 20000000
306#define CONFIG_SF_DEFAULT_MODE 0
307
308/*
309 * General PCI
310 * Memory space is mapped 1-1, but I/O space must start from 0.
311 */
312
313/* controller 1, direct to uli, tgtid 3, Base address 20000 */
314#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
315#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
316#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
317#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
318#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
319#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
320#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
321#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
322
323/* controller 3, Slot 1, tgtid 1, Base address 202000 */
324#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
325#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
326#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
327#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
328#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
329#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
330#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
331#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
332
333/* Qman/Bman */
334#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
335#define CONFIG_SYS_BMAN_NUM_PORTALS 10
336#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
337#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
338#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
339#define CONFIG_SYS_QMAN_NUM_PORTALS 10
340#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
341#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
342#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
343
344#define CONFIG_SYS_DPAA_FMAN
345#define CONFIG_SYS_DPAA_PME
346/* Default address of microcode for the Linux Fman driver
347 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
348 * ucode is stored after env, so we got 0x120000.
349 */
350#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800351#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200352#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
353#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
354
355#define CONFIG_FMAN_ENET
356#define CONFIG_PHYLIB_10G
357#define CONFIG_PHY_MARVELL /* there is a marvell phy */
358
359#define CONFIG_PCI_INDIRECT_BRIDGE
360#define CONFIG_PCI_PNP /* do pci plug-and-play */
361#define CONFIG_E1000
362
363#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
364#define CONFIG_DOS_PARTITION
365
366/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
367#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
368#define CONFIG_SYS_TBIPA_VALUE 8
369#define CONFIG_PHYLIB /* recommended PHY management */
370#define CONFIG_ETHPRIME "FM1@DTSEC5"
371#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
372
373/*
374 * Environment
375 */
376#define CONFIG_LOADS_ECHO /* echo on for serial download */
377#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
378
379/*
Boschung, Rainer88ac6ff2014-06-03 09:05:16 +0200380 * Hardware Watchdog
381 */
382#define CONFIG_WATCHDOG /* enable CPU watchdog */
383#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
384#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
385
386
387/*
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200388 * additionnal command line configuration.
389 */
390#define CONFIG_CMD_PCI
391#define CONFIG_CMD_NET
Valentin Longchamp522641a2014-04-30 15:01:49 +0200392#define CONFIG_CMD_ERRATA
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200393
394/* we don't need flash support */
395#define CONFIG_SYS_NO_FLASH
396#undef CONFIG_CMD_IMLS
397#undef CONFIG_CMD_FLASH
398#undef CONFIG_FLASH_CFI_MTD
399#undef CONFIG_JFFS2_CMDLINE
400
401/*
402 * For booting Linux, the board info and command line data
403 * have to be in the first 64 MB of memory, since this is
404 * the maximum mapped by the Linux kernel during initialization.
405 */
406#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
407#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
408
409#ifdef CONFIG_CMD_KGDB
410#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200411#endif
412
413#define __USB_PHY_TYPE utmi
414
415/*
416 * Environment Configuration
417 */
418#define CONFIG_ENV_OVERWRITE
419#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
420#define CONFIG_KM_DEF_ENV "km-common=empty\0"
421#endif
422
423#ifndef MTDIDS_DEFAULT
424# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
425#endif /* MTDIDS_DEFAULT */
426
427#ifndef MTDPARTS_DEFAULT
428# define MTDPARTS_DEFAULT "mtdparts=" \
429 "fsl_elbc_nand:" \
430 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
431#endif /* MTDPARTS_DEFAULT */
432
433/* architecture specific default bootargs */
434#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
435
436/* FIXME: FDT_ADDR is unspecified */
437#define CONFIG_KM_DEF_ENV_CPU \
438 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
439 "cramfsloadfdt=" \
440 "cramfsload ${fdt_addr_r} " \
441 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
442 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
443 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
444 "update=" \
445 "sf probe 0;sf erase 0 +${filesize};" \
446 "sf write ${load_addr_r} 0 ${filesize};\0" \
Gerlando Falautob1c2a7a2014-01-27 16:58:28 +0100447 "set_fdthigh=true\0" \
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200448 ""
449
450#define CONFIG_HW_ENV_SETTINGS \
451 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
452 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
453 "usb_dr_mode=host\0"
454
455#define CONFIG_KM_NEW_ENV \
456 "newenv=sf probe 0;" \
457 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
458 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
459
460/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
461#ifndef CONFIG_KM_DEF_ARCH
462#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
463#endif
464
465#define CONFIG_EXTRA_ENV_SETTINGS \
466 CONFIG_KM_DEF_ENV \
467 CONFIG_KM_DEF_ARCH \
468 CONFIG_KM_NEW_ENV \
469 CONFIG_HW_ENV_SETTINGS \
470 "EEprom_ivm=pca9547:70:9\0" \
471 ""
472
473#endif /* _CONFIG_KMP204X_H */