blob: a72e1f3567d22144383bf94b306bfb0c5f1112cb [file] [log] [blame]
York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
10#define CONFIG_SYS_GENERIC_BOARD
11
12#define CONFIG_REMAKE_ELF
13#define CONFIG_FSL_LSCH3
14#define CONFIG_LS2085A
15#define CONFIG_GICV3
16
17/* Link Definitions */
York Sun8aeb8932014-09-08 12:20:02 -070018#define CONFIG_SYS_TEXT_BASE 0x30001000
York Sunf749db32014-06-23 15:15:56 -070019
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053020#ifdef CONFIG_EMU
York Sunf749db32014-06-23 15:15:56 -070021#define CONFIG_SYS_NO_FLASH
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053022#endif
York Sunf749db32014-06-23 15:15:56 -070023
24#define CONFIG_SUPPORT_RAW_INITRD
25
26#define CONFIG_SKIP_LOWLEVEL_INIT
27#define CONFIG_BOARD_EARLY_INIT_F 1
28
29#define CONFIG_IDENT_STRING " LS2085A-EMU"
30#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
31
32/* Flat Device Tree Definitions */
33#define CONFIG_OF_LIBFDT
34#define CONFIG_OF_BOARD_SETUP
35
36/* new uImage format support */
37#define CONFIG_FIT
38#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
39
40#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
41#ifndef CONFIG_SYS_FSL_DDR4
42#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
43#define CONFIG_SYS_DDR_RAW_TIMING
44#endif
45#define CONFIG_DIMM_SLOTS_PER_CTLR 1
46#define CONFIG_CHIP_SELECTS_PER_CTRL 4
47
48#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
49
York Sunf749db32014-06-23 15:15:56 -070050#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
51#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
52#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
53#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sund9c68b12014-08-13 10:21:05 -070054#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
55
York Sun8bfa3012014-09-08 12:20:01 -070056/*
57 * SMP Definitinos
58 */
59#define CPU_RELEASE_ADDR secondary_boot_func
60
York Sund9c68b12014-08-13 10:21:05 -070061#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
62#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
63/*
64 * DDR controller use 0 as the base address for binding.
65 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
66 */
67#define CONFIG_SYS_DP_DDR_BASE_PHY 0
68#define CONFIG_DP_DDR_CTRL 2
69#define CONFIG_DP_DDR_NUM_CTRLS 1
70#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
York Sunf749db32014-06-23 15:15:56 -070071
72/* Generic Timer Definitions */
73#define COUNTER_FREQUENCY 12000000 /* 12MHz */
74
75/* Size of malloc() pool */
76#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
77
78/* I2C */
79#define CONFIG_CMD_I2C
80#define CONFIG_SYS_I2C
81#define CONFIG_SYS_I2C_MXC
82#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
83#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
84
85/* Serial Port */
86#define CONFIG_CONS_INDEX 2
87#define CONFIG_SYS_NS16550
88#define CONFIG_SYS_NS16550_SERIAL
89#define CONFIG_SYS_NS16550_REG_SIZE 1
90#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
91
92#define CONFIG_BAUDRATE 115200
93#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
94
95/* IFC */
96#define CONFIG_FSL_IFC
97#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
98#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
99/*
100 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
101 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
102 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
103 * CONFIG_SYS_FLASH_BASE has the final address (core view)
104 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
105 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
106 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
107 */
108#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
109#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
110#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
111
112/*
113 * NOR Flash Timing Params
114 */
115#define CONFIG_SYS_NOR0_CSPR \
116 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
117 CSPR_PORT_SIZE_16 | \
118 CSPR_MSEL_NOR | \
119 CSPR_V)
120#define CONFIG_SYS_NOR0_CSPR_EARLY \
121 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
122 CSPR_PORT_SIZE_16 | \
123 CSPR_MSEL_NOR | \
124 CSPR_V)
125#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
126#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
127 FTIM0_NOR_TEADC(0x1) | \
128 FTIM0_NOR_TEAHC(0x1))
129#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
130 FTIM1_NOR_TRAD_NOR(0x1))
131#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
132 FTIM2_NOR_TCH(0x0) | \
133 FTIM2_NOR_TWP(0x1))
134#define CONFIG_SYS_NOR_FTIM3 0x04000000
135#define CONFIG_SYS_IFC_CCR 0x01000000
136
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530137#ifndef CONFIG_SYS_NO_FLASH
138#define CONFIG_FLASH_CFI_DRIVER
139#define CONFIG_SYS_FLASH_CFI
140#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
141#define CONFIG_SYS_FLASH_QUIET_TEST
142#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
143
144#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
145#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
146#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
148
149#define CONFIG_SYS_FLASH_EMPTY_INFO
150#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
151#endif
152
153#define CONFIG_NAND_FSL_IFC
154#define CONFIG_SYS_NAND_MAX_ECCPOS 256
155#define CONFIG_SYS_NAND_MAX_OOBFREE 2
156#define CONFIG_SYS_NAND_BASE 0x520000000
157#define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
158
159#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
160#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
161 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
162 | CSPR_MSEL_NAND /* MSEL = NAND */ \
163 | CSPR_V)
164#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
165
166#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
167 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
168 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
169 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
170 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
171 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
172 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
173
174#define CONFIG_SYS_NAND_ONFI_DETECTION
175
176/* ONFI NAND Flash mode0 Timing Params */
177#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
178 FTIM0_NAND_TWP(0x18) | \
179 FTIM0_NAND_TWCHT(0x07) | \
180 FTIM0_NAND_TWH(0x0a))
181#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
182 FTIM1_NAND_TWBE(0x39) | \
183 FTIM1_NAND_TRR(0x0e) | \
184 FTIM1_NAND_TRP(0x18))
185#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
186 FTIM2_NAND_TREH(0x0a) | \
187 FTIM2_NAND_TWHRE(0x1e))
188#define CONFIG_SYS_NAND_FTIM3 0x0
189
190#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
191#define CONFIG_SYS_MAX_NAND_DEVICE 1
192#define CONFIG_MTD_NAND_VERIFY_WRITE
193#define CONFIG_CMD_NAND
194
195#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
196
York Sunf749db32014-06-23 15:15:56 -0700197#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
198#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
199#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
200#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
201#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
202#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
203#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
204#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
205#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
206
207/* MC firmware */
208#define CONFIG_FSL_MC_ENET
209#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
210#define CONFIG_SYS_LS_MC_FW_IN_NOR
211#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
212/* TODO Actual FW length needs to be determined at runtime from FW header */
213#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024)
214#define CONFIG_SYS_LS_MC_DPL_IN_NOR
215#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
216/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
217#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096
218#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
219
220/* Carve the MC private DRAM block from the end of DRAM */
221#ifdef CONFIG_FSL_MC_ENET
222#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size()
223#endif
224
225/* Command line configuration */
226#define CONFIG_CMD_CACHE
227#define CONFIG_CMD_BDI
228#define CONFIG_CMD_DHCP
229#define CONFIG_CMD_ENV
230#define CONFIG_CMD_FLASH
231#define CONFIG_CMD_IMI
232#define CONFIG_CMD_MEMORY
233#define CONFIG_CMD_MII
234#define CONFIG_CMD_NET
235#define CONFIG_CMD_PING
236#define CONFIG_CMD_SAVEENV
237#define CONFIG_CMD_RUN
238#define CONFIG_CMD_BOOTD
239#define CONFIG_CMD_ECHO
240#define CONFIG_CMD_SOURCE
241#define CONFIG_CMD_FAT
242#define CONFIG_DOS_PARTITION
243
244/* Miscellaneous configurable options */
245#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
York Sun8bfa3012014-09-08 12:20:01 -0700246#define CONFIG_ARCH_EARLY_INIT_R
York Sunf749db32014-06-23 15:15:56 -0700247
248/* Physical Memory Map */
249/* fixme: these need to be checked against the board */
250#define CONFIG_CHIP_SELECTS_PER_CTRL 4
251#define CONFIG_SYS_CLK_FREQ 133333333
252
253
York Sund9c68b12014-08-13 10:21:05 -0700254#define CONFIG_NR_DRAM_BANKS 3
York Sunf749db32014-06-23 15:15:56 -0700255
256#define CONFIG_SYS_HZ 1000
257
258#define CONFIG_HWCONFIG
259#define HWCONFIG_BUFFER_SIZE 128
260
261#define CONFIG_DISPLAY_CPUINFO
262
263/* Initial environment variables */
264#define CONFIG_EXTRA_ENV_SETTINGS \
265 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
266 "loadaddr=0x80100000\0" \
267 "kernel_addr=0x100000\0" \
268 "ramdisk_addr=0x800000\0" \
269 "ramdisk_size=0x2000000\0" \
270 "fdt_high=0xffffffffffffffff\0" \
271 "initrd_high=0xffffffffffffffff\0" \
272 "kernel_start=0x581200000\0" \
273 "kernel_load=0x806f0000\0" \
274 "kernel_size=0x1000000\0" \
275 "console=ttyAMA0,38400n8\0"
276
277#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
278 "earlyprintk=uart8250-8bit,0x21c0600"
279#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
280 "$kernel_size && bootm $kernel_load"
281#define CONFIG_BOOTDELAY 1
282
283/* Store environment at top of flash */
284#define CONFIG_ENV_IS_NOWHERE 1
285#define CONFIG_ENV_SIZE 0x1000
286
287/* Monitor Command Prompt */
288#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
289#define CONFIG_SYS_PROMPT "> "
290#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
291 sizeof(CONFIG_SYS_PROMPT) + 16)
292#define CONFIG_SYS_HUSH_PARSER
293#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
294#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
295#define CONFIG_SYS_LONGHELP
296#define CONFIG_CMDLINE_EDITING 1
297#define CONFIG_SYS_MAXARGS 64 /* max command args */
298
299#ifndef __ASSEMBLY__
300unsigned long mc_get_dram_block_size(void);
301#endif
302
303#endif /* __LS2_COMMON_H */