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wdenk1df49e22002-09-17 21:37:55 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * cpu.c
26 *
27 * CPU specific code
28 *
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
31 *
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
34 *
35 * more modifications by
36 * Josh Huber <huber@mclx.com>
37 * added support for the 74xx series of cpus
38 * added support for the 7xx series of cpus
39 * made the code a little less hard-coded, and more auto-detectish
40 */
41
42#include <common.h>
43#include <command.h>
44#include <74xx_7xx.h>
45#include <asm/cache.h>
46
Gerald Van Baren589c0422008-06-03 20:24:58 -040047#if defined(CONFIG_OF_LIBFDT)
48#include <libfdt.h>
49#include <fdt_support.h>
50#endif
51
wdenkc7de8292002-11-19 11:04:11 +000052#ifdef CONFIG_AMIGAONEG3SE
53#include "../board/MAI/AmigaOneG3SE/via686.h"
54#include "../board/MAI/AmigaOneG3SE/memio.h"
55#endif
56
Wolfgang Denkd87080b2006-03-31 18:32:53 +020057DECLARE_GLOBAL_DATA_PTR;
58
wdenk1df49e22002-09-17 21:37:55 +000059cpu_t
60get_cpu_type(void)
61{
62 uint pvr = get_pvr();
63 cpu_t type;
64
65 type = CPU_UNKNOWN;
66
67 switch (PVR_VER(pvr)) {
68 case 0x000c:
69 type = CPU_7400;
70 break;
71 case 0x0008:
72 type = CPU_750;
73
wdenk72755c72003-06-20 23:10:58 +000074 if (((pvr >> 8) & 0xff) == 0x01) {
wdenk1df49e22002-09-17 21:37:55 +000075 type = CPU_750CX; /* old CX (80100 and 8010x?)*/
76 } else if (((pvr >> 8) & 0xff) == 0x22) {
77 type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
78 } else if (((pvr >> 8) & 0xff) == 0x33) {
79 type = CPU_750CX; /* CXe (83311) */
80 } else if (((pvr >> 12) & 0xF) == 0x3) {
81 type = CPU_755;
wdenk72755c72003-06-20 23:10:58 +000082 }
83 break;
84
85 case 0x7000:
86 type = CPU_750FX;
wdenk1df49e22002-09-17 21:37:55 +000087 break;
88
wdenk3a473b22004-01-03 00:43:19 +000089 case 0x7002:
90 type = CPU_750GX;
91 break;
92
wdenk1df49e22002-09-17 21:37:55 +000093 case 0x800C:
94 type = CPU_7410;
95 break;
96
wdenk72755c72003-06-20 23:10:58 +000097 case 0x8000:
wdenk1df49e22002-09-17 21:37:55 +000098 type = CPU_7450;
99 break;
100
wdenk3a473b22004-01-03 00:43:19 +0000101 case 0x8001:
102 type = CPU_7455;
103 break;
104
105 case 0x8002:
106 type = CPU_7457;
107 break;
108
roy zang4c527832006-11-02 18:49:51 +0800109 case 0x8003:
110 type = CPU_7447A;
111 break;
roy zangc9c1eee2006-12-01 19:01:25 +0800112
roy zang4c527832006-11-02 18:49:51 +0800113 case 0x8004:
114 type = CPU_7448;
115 break;
roy zangc9c1eee2006-12-01 19:01:25 +0800116
wdenk1df49e22002-09-17 21:37:55 +0000117 default:
118 break;
119 }
120
121 return type;
122}
123
124/* ------------------------------------------------------------------------- */
125
126#if !defined(CONFIG_BAB7xx)
127int checkcpu (void)
128{
wdenk1df49e22002-09-17 21:37:55 +0000129 uint type = get_cpu_type();
130 uint pvr = get_pvr();
131 ulong clock = gd->cpu_clk;
132 char buf[32];
133 char *str;
134
135 puts ("CPU: ");
136
137 switch (type) {
138 case CPU_750CX:
139 printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
140 (pvr>>8) & 0xf,
141 pvr & 0xf);
142 goto PR_CLK;
143
144 case CPU_750:
145 str = "750";
146 break;
147
wdenk72755c72003-06-20 23:10:58 +0000148 case CPU_750FX:
149 str = "750FX";
150 break;
151
wdenk3a473b22004-01-03 00:43:19 +0000152 case CPU_750GX:
153 str = "750GX";
154 break;
155
wdenk1df49e22002-09-17 21:37:55 +0000156 case CPU_755:
157 str = "755";
158 break;
159
160 case CPU_7400:
161 str = "MPC7400";
162 break;
163
wdenk72755c72003-06-20 23:10:58 +0000164 case CPU_7410:
165 str = "MPC7410";
wdenk1df49e22002-09-17 21:37:55 +0000166 break;
167
roy zangc9c1eee2006-12-01 19:01:25 +0800168 case CPU_7447A:
169 str = "MPC7447A";
170 break;
171
Stefan Roese1eac2a72006-11-29 15:42:37 +0100172 case CPU_7448:
173 str = "MPC7448";
174 break;
175
wdenk72755c72003-06-20 23:10:58 +0000176 case CPU_7450:
177 str = "MPC7450";
wdenk1df49e22002-09-17 21:37:55 +0000178 break;
179
wdenk3a473b22004-01-03 00:43:19 +0000180 case CPU_7455:
181 str = "MPC7455";
182 break;
183
184 case CPU_7457:
185 str = "MPC7457";
186 break;
187
wdenk1df49e22002-09-17 21:37:55 +0000188 default:
wdenk72755c72003-06-20 23:10:58 +0000189 printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
wdenk1df49e22002-09-17 21:37:55 +0000190 return -1;
191 }
192
193 printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
194PR_CLK:
195 printf (" @ %s MHz\n", strmhz(buf, clock));
196
197 return (0);
198}
199#endif
200/* these two functions are unimplemented currently [josh] */
201
wdenk72755c72003-06-20 23:10:58 +0000202/* -------------------------------------------------------------------- */
203/* L1 i-cache */
wdenk1df49e22002-09-17 21:37:55 +0000204
205int
206checkicache(void)
207{
208 return 0; /* XXX */
209}
210
wdenk72755c72003-06-20 23:10:58 +0000211/* -------------------------------------------------------------------- */
212/* L1 d-cache */
wdenk1df49e22002-09-17 21:37:55 +0000213
214int
215checkdcache(void)
216{
217 return 0; /* XXX */
218}
219
wdenk72755c72003-06-20 23:10:58 +0000220/* -------------------------------------------------------------------- */
wdenk1df49e22002-09-17 21:37:55 +0000221
222static inline void
223soft_restart(unsigned long addr)
224{
225 /* SRR0 has system reset vector, SRR1 has default MSR value */
226 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
227
228 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
229 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
230 __asm__ __volatile__ ("mtspr 27, 4");
231 __asm__ __volatile__ ("rfi");
232
233 while(1); /* not reached */
234}
235
236
237#if !defined(CONFIG_PCIPPC2) && \
238 !defined(CONFIG_BAB7xx) && \
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200239 !defined(CONFIG_ELPPC) && \
240 !defined(CONFIG_PPMC7XX)
wdenk1df49e22002-09-17 21:37:55 +0000241/* no generic way to do board reset. simply call soft_reset. */
242void
wdenk8bde7f72003-06-27 21:31:46 +0000243do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenk1df49e22002-09-17 21:37:55 +0000244{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100245 ulong addr;
wdenk1df49e22002-09-17 21:37:55 +0000246 /* flush and disable I/D cache */
247 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
248 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
249 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
250 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
251 __asm__ __volatile__ ("sync");
252 __asm__ __volatile__ ("mtspr 1008, 4");
253 __asm__ __volatile__ ("isync");
254 __asm__ __volatile__ ("sync");
255 __asm__ __volatile__ ("mtspr 1008, 5");
256 __asm__ __volatile__ ("isync");
257 __asm__ __volatile__ ("sync");
258
259#ifdef CFG_RESET_ADDRESS
260 addr = CFG_RESET_ADDRESS;
261#else
262 /*
263 * note: when CFG_MONITOR_BASE points to a RAM address,
264 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
265 * address. Better pick an address known to be invalid on your
266 * system and assign it to CFG_RESET_ADDRESS.
267 */
268 addr = CFG_MONITOR_BASE - sizeof (ulong);
269#endif
270 soft_restart(addr);
271 while(1); /* not reached */
272}
273#endif
274
275/* ------------------------------------------------------------------------- */
276
277/*
278 * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
279 */
roy zang4c527832006-11-02 18:49:51 +0800280#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
wdenkc7de8292002-11-19 11:04:11 +0000281unsigned long get_tbclk(void)
282{
wdenkc7de8292002-11-19 11:04:11 +0000283 return (gd->bus_clk / 4);
284}
roy zang4c527832006-11-02 18:49:51 +0800285#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
wdenkc7de8292002-11-19 11:04:11 +0000286
287unsigned long get_tbclk (void)
wdenk1df49e22002-09-17 21:37:55 +0000288{
289 return CFG_BUS_HZ / 4;
290}
roy zang4c527832006-11-02 18:49:51 +0800291#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
wdenk1df49e22002-09-17 21:37:55 +0000292/* ------------------------------------------------------------------------- */
wdenk1df49e22002-09-17 21:37:55 +0000293#if defined(CONFIG_WATCHDOG)
294#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
295void
296watchdog_reset(void)
297{
298
299}
300#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
301#endif /* CONFIG_WATCHDOG */
302
303/* ------------------------------------------------------------------------- */
roy zang4c527832006-11-02 18:49:51 +0800304
Gerald Van Baren589c0422008-06-03 20:24:58 -0400305#ifdef CONFIG_OF_LIBFDT
306void ft_cpu_setup(void *blob, bd_t *bd)
roy zang4c527832006-11-02 18:49:51 +0800307{
Gerald Van Baren589c0422008-06-03 20:24:58 -0400308 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
309 "timebase-frequency", bd->bi_busfreq / 4, 1);
310 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
311 "bus-frequency", bd->bi_busfreq, 1);
312 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
313 "clock-frequency", bd->bi_intfreq, 1);
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100314
Gerald Van Baren589c0422008-06-03 20:24:58 -0400315 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100316
Gerald Van Baren589c0422008-06-03 20:24:58 -0400317 fdt_fixup_ethernet(blob, bd);
roy zang4c527832006-11-02 18:49:51 +0800318}
319#endif
320/* ------------------------------------------------------------------------- */