blob: 87ca6ef4bef24687e74e50ffd997fe4d37f3a173 [file] [log] [blame]
wdenk7d393ae2002-10-25 21:08:05 +00001/*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 *
24 * TODO: clean-up
25 */
26
27#include <common.h>
28#include "pip405.h"
29#include <asm/processor.h>
30#include <i2c.h>
31#include "../common/isa.h"
32#include "../common/common_util.h"
33
34#undef SDRAM_DEBUG
35
36#define FALSE 0
37#define TRUE 1
38
39/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
40#ifndef __ldiv_t_defined
41typedef struct {
42 long int quot; /* Quotient */
43 long int rem; /* Remainder */
44} ldiv_t;
45extern ldiv_t ldiv (long int __numer, long int __denom);
46
47# define __ldiv_t_defined 1
48#endif
49
50
51typedef enum {
52 SDRAM_NO_ERR,
53 SDRAM_SPD_COMM_ERR,
54 SDRAM_SPD_CHKSUM_ERR,
55 SDRAM_UNSUPPORTED_ERR,
56 SDRAM_UNKNOWN_ERR
57} SDRAM_ERR;
58
59typedef struct {
60 const unsigned char mode;
61 const unsigned char row;
62 const unsigned char col;
63 const unsigned char bank;
64} SDRAM_SETUP;
65
66static const SDRAM_SETUP sdram_setup_table[] = {
67 {1, 11, 9, 2},
68 {1, 11, 10, 2},
69 {2, 12, 9, 4},
70 {2, 12, 10, 4},
71 {3, 13, 9, 4},
72 {3, 13, 10, 4},
73 {3, 13, 11, 4},
74 {4, 12, 8, 2},
75 {4, 12, 8, 4},
76 {5, 11, 8, 2},
77 {5, 11, 8, 4},
78 {6, 13, 8, 2},
79 {6, 13, 8, 4},
80 {7, 13, 9, 2},
81 {7, 13, 10, 2},
82 {0, 0, 0, 0}
83};
84
85static const unsigned char cal_indextable[] = {
86 9, 23, 25
87};
88
89
90/*
91 * translate ns.ns/10 coding of SPD timing values
92 * into 10 ps unit values
93 */
94
95unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
96{
97 unsigned short ns, ns10;
98
99 /* isolate upper nibble */
100 ns = (spd_byte >> 4) & 0x0F;
101 /* isolate lower nibble */
102 ns10 = (spd_byte & 0x0F);
103
104 return (ns * 100 + ns10 * 10);
105}
106
107/*
108 * translate ns.ns/4 coding of SPD timing values
109 * into 10 ps unit values
110 */
111
112unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
113{
114 unsigned short ns, ns4;
115
116 /* isolate upper 6 bits */
117 ns = (spd_byte >> 2) & 0x3F;
118 /* isloate lower 2 bits */
119 ns4 = (spd_byte & 0x03);
120
121 return (ns * 100 + ns4 * 25);
122}
123
124/*
125 * translate ns coding of SPD timing values
126 * into 10 ps unit values
127 */
128
129unsigned short NSto10PS (unsigned char spd_byte)
130{
131 return (spd_byte * 100);
132}
133
134void SDRAM_err (const char *s)
135{
136#ifndef SDRAM_DEBUG
137 DECLARE_GLOBAL_DATA_PTR;
138
139 (void) get_clocks ();
140 gd->baudrate = 9600;
141 serial_init ();
142#endif
143 serial_puts ("\n");
144 serial_puts (s);
145 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
146 for (;;);
147}
148
149
150#ifdef SDRAM_DEBUG
151
152void write_hex (unsigned char i)
153{
154 char cc;
155
156 cc = i >> 4;
157 cc &= 0xf;
158 if (cc > 9)
159 serial_putc (cc + 55);
160 else
161 serial_putc (cc + 48);
162 cc = i & 0xf;
163 if (cc > 9)
164 serial_putc (cc + 55);
165 else
166 serial_putc (cc + 48);
167}
168
169void write_4hex (unsigned long val)
170{
171 write_hex ((unsigned char) (val >> 24));
172 write_hex ((unsigned char) (val >> 16));
173 write_hex ((unsigned char) (val >> 8));
174 write_hex ((unsigned char) val);
175}
176
177#endif
178
179int board_pre_init (void)
180{
181 unsigned char dataout[1];
182 unsigned char datain[128];
183 unsigned long sdram_size;
184 SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
185 unsigned long memclk;
186 unsigned long tmemclk = 0;
187 unsigned long tmp, bank, baseaddr, bank_size;
188 unsigned short i;
189 unsigned char rows, cols, banks, sdram_banks, density;
190 unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
191 trc_clocks, tctp_clocks;
192 unsigned char cal_index, cal_val, spd_version, spd_chksum;
193 unsigned char buf[8];
194#ifdef SDRAM_DEBUG
195 DECLARE_GLOBAL_DATA_PTR;
196#endif
197
198 memclk = get_bus_freq (tmemclk);
199 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
200
201#ifdef SDRAM_DEBUG
202 (void) get_clocks ();
203 gd->baudrate = 9600;
204 serial_init ();
205 serial_puts ("\nstart SDRAM Setup\n");
206#endif
207
208 /* Read Serial Presence Detect Information */
209 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
210 dataout[0] = 0;
211 for (i = 0; i < 128; i++)
212 datain[i] = 127;
213 i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
214#ifdef SDRAM_DEBUG
215 serial_puts ("\ni2c_read returns ");
216 write_hex (i);
217 serial_puts ("\n");
218#endif
219
220#ifdef SDRAM_DEBUG
221 for (i = 0; i < 128; i++) {
222 write_hex (datain[i]);
223 serial_puts (" ");
224 if (((i + 1) % 16) == 0)
225 serial_puts ("\n");
226 }
227 serial_puts ("\n");
228#endif
229 spd_chksum = 0;
230 for (i = 0; i < 63; i++) {
231 spd_chksum += datain[i];
232 } /* endfor */
233 if (datain[63] != spd_chksum) {
234#ifdef SDRAM_DEBUG
235 serial_puts ("SPD chksum: 0x");
236 write_hex (datain[63]);
237 serial_puts (" != calc. chksum: 0x");
238 write_hex (spd_chksum);
239 serial_puts ("\n");
240#endif
241 SDRAM_err ("SPD checksum Error");
242 }
243 /* SPD seems to be ok, use it */
244
245 /* get SPD version */
246 spd_version = datain[62];
247
248 /* do some sanity checks on the kind of RAM */
249 if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
250 (datain[2] != 0x04) || /* if not SDRAM */
251 (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
252 (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
253 (datain[126] == 0x66)) /* or a 66Mhz modules */
254 SDRAM_err ("unsupported SDRAM");
255#ifdef SDRAM_DEBUG
256 serial_puts ("SDRAM sanity ok\n");
257#endif
258
259 /* get number of rows/cols/banks out of byte 3+4+5 */
260 rows = datain[3];
261 cols = datain[4];
262 banks = datain[5];
263
264 /* get number of SDRAM banks out of byte 17 and
265 supported CAS latencies out of byte 18 */
266 sdram_banks = datain[17];
267 supported_cal = datain[18] & ~0x81;
268
269 while (t->mode != 0) {
270 if ((t->row == rows) && (t->col == cols)
271 && (t->bank == sdram_banks))
272 break;
273 t++;
274 } /* endwhile */
275
276#ifdef SDRAM_DEBUG
277 serial_puts ("rows: ");
278 write_hex (rows);
279 serial_puts (" cols: ");
280 write_hex (cols);
281 serial_puts (" banks: ");
282 write_hex (banks);
283 serial_puts (" mode: ");
284 write_hex (t->mode);
285 serial_puts ("\n");
286#endif
287 if (t->mode == 0)
288 SDRAM_err ("unsupported SDRAM");
289 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
290#ifdef SDRAM_DEBUG
291 serial_puts ("tRP: ");
292 write_hex (datain[27]);
293 serial_puts ("\ntRCD: ");
294 write_hex (datain[29]);
295 serial_puts ("\ntRAS: ");
296 write_hex (datain[30]);
297 serial_puts ("\n");
298#endif
299
300 trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
301 trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
302 tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
303 density = datain[31];
304
305 /* trc_clocks is sum of trp_clocks + tras_clocks */
306 trc_clocks = trp_clocks + tras_clocks;
307 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
308 tctp_clocks =
309 ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
310 (tmemclk - 1)) / tmemclk;
311
312#ifdef SDRAM_DEBUG
313 serial_puts ("c_RP: ");
314 write_hex (trp_clocks);
315 serial_puts ("\nc_RCD: ");
316 write_hex (trcd_clocks);
317 serial_puts ("\nc_RAS: ");
318 write_hex (tras_clocks);
319 serial_puts ("\nc_RC: (RP+RAS): ");
320 write_hex (trc_clocks);
321 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
322 write_hex (tctp_clocks);
323 serial_puts ("\nt_CTP: RAS - RCD: ");
324 write_hex ((unsigned
325 char) ((NSto10PS (datain[30]) -
326 NSto10PS (datain[29])) >> 8));
327 write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
328 serial_puts ("\ntmemclk: ");
329 write_hex ((unsigned char) (tmemclk >> 8));
330 write_hex ((unsigned char) (tmemclk));
331 serial_puts ("\n");
332#endif
333
334
335 cal_val = 255;
336 for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
337 /* is this CAS latency supported ? */
338 if ((supported_cal >> i) & 0x01) {
339 buf[0] = datain[cal_indextable[cal_index]];
340 if (cal_index < 2) {
341 if (NS10to10PS (buf[0], spd_version) <= tmemclk)
342 cal_val = i;
343 } else {
344 /* SPD bytes 25+26 have another format */
345 if (NS4to10PS (buf[0], spd_version) <= tmemclk)
346 cal_val = i;
347 } /* endif */
348 cal_index++;
349 } /* endif */
350 } /* endfor */
351#ifdef SDRAM_DEBUG
352 serial_puts ("CAL: ");
353 write_hex (cal_val + 1);
354 serial_puts ("\n");
355#endif
356
357 if (cal_val == 255)
358 SDRAM_err ("unsupported SDRAM");
359
360 /* get SDRAM timing register */
361 mtdcr (memcfga, mem_sdtr1);
362 tmp = mfdcr (memcfgd) & ~0x018FC01F;
363 /* insert CASL value */
364/* tmp |= ((unsigned long)cal_val) << 23; */
365 tmp |= ((unsigned long) cal_val) << 23;
366 /* insert PTA value */
367 tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
368 /* insert CTP value */
369/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
370 tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
371 /* insert LDF (always 01) */
372 tmp |= ((unsigned long) 0x01) << 14;
373 /* insert RFTA value */
374 tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
375 /* insert RCD value */
376 tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
377
378#ifdef SDRAM_DEBUG
379 serial_puts ("sdtr: ");
380 write_4hex (tmp);
381 serial_puts ("\n");
382#endif
383
384 /* write SDRAM timing register */
385 mtdcr (memcfga, mem_sdtr1);
386 mtdcr (memcfgd, tmp);
387 baseaddr = CFG_SDRAM_BASE;
388 bank_size = (((unsigned long) density) << 22) / 2;
389 /* insert AM value */
390 tmp = ((unsigned long) t->mode - 1) << 13;
391 /* insert SZ value; */
392 switch (bank_size) {
393 case 0x00400000:
394 tmp |= ((unsigned long) 0x00) << 17;
395 break;
396 case 0x00800000:
397 tmp |= ((unsigned long) 0x01) << 17;
398 break;
399 case 0x01000000:
400 tmp |= ((unsigned long) 0x02) << 17;
401 break;
402 case 0x02000000:
403 tmp |= ((unsigned long) 0x03) << 17;
404 break;
405 case 0x04000000:
406 tmp |= ((unsigned long) 0x04) << 17;
407 break;
408 case 0x08000000:
409 tmp |= ((unsigned long) 0x05) << 17;
410 break;
411 case 0x10000000:
412 tmp |= ((unsigned long) 0x06) << 17;
413 break;
414 default:
415 SDRAM_err ("unsupported SDRAM");
416 } /* endswitch */
417 /* get SDRAM bank 0 register */
418 mtdcr (memcfga, mem_mb0cf);
419 bank = mfdcr (memcfgd) & ~0xFFCEE001;
420 bank |= (baseaddr | tmp | 0x01);
421#ifdef SDRAM_DEBUG
422 serial_puts ("bank0: baseaddr: ");
423 write_4hex (baseaddr);
424 serial_puts (" banksize: ");
425 write_4hex (bank_size);
426 serial_puts (" mb0cf: ");
427 write_4hex (bank);
428 serial_puts ("\n");
429#endif
430 baseaddr += bank_size;
431 sdram_size += bank_size;
432
433 /* write SDRAM bank 0 register */
434 mtdcr (memcfga, mem_mb0cf);
435 mtdcr (memcfgd, bank);
436
437 /* get SDRAM bank 1 register */
438 mtdcr (memcfga, mem_mb1cf);
439 bank = mfdcr (memcfgd) & ~0xFFCEE001;
440 sdram_size = 0;
441
442#ifdef SDRAM_DEBUG
443 serial_puts ("bank1: baseaddr: ");
444 write_4hex (baseaddr);
445 serial_puts (" banksize: ");
446 write_4hex (bank_size);
447#endif
448 if (banks == 2) {
449 bank |= (baseaddr | tmp | 0x01);
450 baseaddr += bank_size;
451 sdram_size += bank_size;
452 } /* endif */
453#ifdef SDRAM_DEBUG
454 serial_puts (" mb1cf: ");
455 write_4hex (bank);
456 serial_puts ("\n");
457#endif
458 /* write SDRAM bank 1 register */
459 mtdcr (memcfga, mem_mb1cf);
460 mtdcr (memcfgd, bank);
461
462 /* get SDRAM bank 2 register */
463 mtdcr (memcfga, mem_mb2cf);
464 bank = mfdcr (memcfgd) & ~0xFFCEE001;
465
466 bank |= (baseaddr | tmp | 0x01);
467
468#ifdef SDRAM_DEBUG
469 serial_puts ("bank2: baseaddr: ");
470 write_4hex (baseaddr);
471 serial_puts (" banksize: ");
472 write_4hex (bank_size);
473 serial_puts (" mb2cf: ");
474 write_4hex (bank);
475 serial_puts ("\n");
476#endif
477
478 baseaddr += bank_size;
479 sdram_size += bank_size;
480
481 /* write SDRAM bank 2 register */
482 mtdcr (memcfga, mem_mb2cf);
483 mtdcr (memcfgd, bank);
484
485 /* get SDRAM bank 3 register */
486 mtdcr (memcfga, mem_mb3cf);
487 bank = mfdcr (memcfgd) & ~0xFFCEE001;
488
489#ifdef SDRAM_DEBUG
490 serial_puts ("bank3: baseaddr: ");
491 write_4hex (baseaddr);
492 serial_puts (" banksize: ");
493 write_4hex (bank_size);
494#endif
495
496 if (banks == 2) {
497 bank |= (baseaddr | tmp | 0x01);
498 baseaddr += bank_size;
499 sdram_size += bank_size;
500 }
501 /* endif */
502#ifdef SDRAM_DEBUG
503 serial_puts (" mb3cf: ");
504 write_4hex (bank);
505 serial_puts ("\n");
506#endif
507
508 /* write SDRAM bank 3 register */
509 mtdcr (memcfga, mem_mb3cf);
510 mtdcr (memcfgd, bank);
511
512
513 /* get SDRAM refresh interval register */
514 mtdcr (memcfga, mem_rtr);
515 tmp = mfdcr (memcfgd) & ~0x3FF80000;
516
517 if (tmemclk < NSto10PS (16))
518 tmp |= 0x05F00000;
519 else
520 tmp |= 0x03F80000;
521
522 /* write SDRAM refresh interval register */
523 mtdcr (memcfga, mem_rtr);
524 mtdcr (memcfgd, tmp);
525
526 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
527 mtdcr (memcfga, mem_mcopt1);
528 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
529 mtdcr (memcfga, mem_mcopt1);
530 mtdcr (memcfgd, tmp);
531
532
533
534 /*-------------------------------------------------------------------------+
535 | Interrupt controller setup for the PIP405 board.
536 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
537 | IRQ 16 405GP internally generated; active low; level sensitive
538 | IRQ 17-24 RESERVED
539 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
540 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
541 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
542 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
543 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
544 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
545 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
546 | Note for PIP405 board:
547 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
548 | the Interrupt Controller in the South Bridge has caused the
549 | interrupt. The IC must be read to determine which device
550 | caused the interrupt.
551 |
552 +-------------------------------------------------------------------------*/
553 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
554 mtdcr (uicer, 0x00000000); /* disable all ints */
555 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
556 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
557 mtdcr (uictr, 0x10000000); /* set int trigger levels */
558 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
559 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
560
561 return 0;
562}
563
564
565/* ------------------------------------------------------------------------- */
566
567/*
568 * Check Board Identity:
569 */
570
571int checkboard (void)
572{
573 unsigned char s[50];
574 unsigned char bc;
575 int i;
576 backup_t *b = (backup_t *) s;
577
578 puts ("Board: ");
579
580 i = getenv_r ("serial#", s, 32);
581 if ((i == 0) || strncmp (s, "PIP405", 6)) {
582 get_backup_values (b);
583 if (strncmp (b->signature, "MPL\0", 4) != 0) {
584 puts ("### No HW ID - assuming PIP405");
585 } else {
586 b->serial_name[6] = 0;
587 printf ("%s SN: %s", b->serial_name,
588 &b->serial_name[7]);
589 }
590 } else {
591 s[6] = 0;
592 printf ("%s SN: %s", s, &s[7]);
593 }
594 bc = in8 (CONFIG_PORT_ADDR);
595 printf (" Boot Config: 0x%x\n", bc);
596 return (0);
597}
598
599
600/* ------------------------------------------------------------------------- */
601/* ------------------------------------------------------------------------- */
602/*
603 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
604 the necessary info for SDRAM controller configuration
605*/
606/* ------------------------------------------------------------------------- */
607/* ------------------------------------------------------------------------- */
608static int test_dram (unsigned long ramsize);
609
610long int initdram (int board_type)
611{
612 DECLARE_GLOBAL_DATA_PTR;
613
614 unsigned long bank_reg[4], tmp, bank_size;
615 int i, ds;
616 unsigned long TotalSize;
617
618 ds = 0;
619 /* since the DRAM controller is allready set up,
620 * calculate the size with the bank registers
621 */
622 mtdcr (memcfga, mem_mb0cf);
623 bank_reg[0] = mfdcr (memcfgd);
624 mtdcr (memcfga, mem_mb1cf);
625 bank_reg[1] = mfdcr (memcfgd);
626 mtdcr (memcfga, mem_mb2cf);
627 bank_reg[2] = mfdcr (memcfgd);
628 mtdcr (memcfga, mem_mb3cf);
629 bank_reg[3] = mfdcr (memcfgd);
630 TotalSize = 0;
631 for (i = 0; i < 4; i++) {
632 if ((bank_reg[i] & 0x1) == 0x1) {
633 tmp = (bank_reg[i] >> 17) & 0x7;
634 bank_size = 4 << tmp;
635 TotalSize += bank_size;
636 } else
637 ds = 1;
638 }
639 if (ds == 1)
640 printf ("single-sided DIMM ");
641 else
642 printf ("double-sided DIMM ");
643 test_dram (TotalSize * 1024 * 1024);
644 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
645 (void) get_clocks();
646 if (gd->cpu_clk > 220000000)
647 TotalSize /= 2;
648 return (TotalSize * 1024 * 1024);
649}
650
651/* ------------------------------------------------------------------------- */
652
653
654static int test_dram (unsigned long ramsize)
655{
656 /* not yet implemented */
657 return (1);
658}
659
660
661int misc_init_r (void)
662{
663 return (0);
664}
665
666/***************************************************************************
667 * some helping routines
668 */
669
670int overwrite_console (void)
671{
672 return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */
673}
674
675
676
677extern int isa_init (void);
678
679
680void print_pip405_rev (void)
681{
682 unsigned char part, vers, cfg;
683
684 part = in8 (PLD_PART_REG);
685 vers = in8 (PLD_VERS_REG);
686 cfg = in8 (PLD_BOARD_CFG_REG);
687 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
688 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
689 vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
690}
691
692extern void check_env(void);
693
694
695int last_stage_init (void)
696{
697 print_pip405_rev ();
698 isa_init ();
699 show_stdio_dev ();
700 check_env();
701 return 0;
702}
703
704/************************************************************************
705* Print PIP405 Info
706************************************************************************/
707void print_pip405_info (void)
708{
709 unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
710 compwr, nicvga, scsirst;
711
712 part = in8 (PLD_PART_REG);
713 vers = in8 (PLD_VERS_REG);
714 cfg = in8 (PLD_BOARD_CFG_REG);
715 ledu = in8 (PLD_LED_USER_REG);
716 sysman = in8 (PLD_SYS_MAN_REG);
717 flashcom = in8 (PLD_FLASH_COM_REG);
718 can = in8 (PLD_CAN_REG);
719 serpwr = in8 (PLD_SER_PWR_REG);
720 compwr = in8 (PLD_COM_PWR_REG);
721 nicvga = in8 (PLD_NIC_VGA_REG);
722 scsirst = in8 (PLD_SCSI_RST_REG);
723 printf ("PLD Part %d version %d\n",
724 part & 0xf, vers & 0xf);
725 printf ("PLD Part %d version %d\n",
726 (part >> 4) & 0xf, (vers >> 4) & 0xf);
727 printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
728 printf ("Population Options %d %d %d %d\n",
729 (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
730 (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
731 printf ("User LED0 %s User LED1 %s\n",
732 ((ledu & 0x1) == 0x1) ? "on" : "off",
733 ((ledu & 0x2) == 0x2) ? "on" : "off");
734 printf ("Additionally Options %d %d\n",
735 (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
736 printf ("User Config Switch %d %d %d %d\n",
737 (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
738 (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
739 switch (sysman & 0x3) {
740 case 0:
741 printf ("PCI Clocks are running\n");
742 break;
743 case 1:
744 printf ("PCI Clocks are stopped in POS State\n");
745 break;
746 case 2:
747 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
748 break;
749 case 3:
750 printf ("PCI Clocks are stopped\n");
751 break;
752 }
753 switch ((sysman >> 2) & 0x3) {
754 case 0:
755 printf ("Main Clocks are running\n");
756 break;
757 case 1:
758 printf ("Main Clocks are stopped in POS State\n");
759 break;
760 case 2:
761 case 3:
762 printf ("PCI Clocks are stopped\n");
763 break;
764 }
765 printf ("INIT asserts %sINT2# (SMI)\n",
766 ((sysman & 0x10) == 0x10) ? "" : "not ");
767 printf ("INIT asserts %sINT1# (NMI)\n",
768 ((sysman & 0x20) == 0x20) ? "" : "not ");
769 printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
770 printf ("SER1 is routed to %s\n",
771 ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
772 printf ("COM2 is routed to %s\n",
773 ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
774 printf ("RS485 is configured as %s duplex\n",
775 ((flashcom & 0x4) == 0x4) ? "full" : "half");
776 printf ("RS485 is connected to %s\n",
777 ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
778 printf ("SER1 uses handshakes %s\n",
779 ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
780 printf ("Bootflash is %swriteprotected\n",
781 ((flashcom & 0x20) == 0x20) ? "not " : "");
782 printf ("Bootflash VPP is %s\n",
783 ((flashcom & 0x40) == 0x40) ? "on" : "off");
784 printf ("Bootsector is %swriteprotected\n",
785 ((flashcom & 0x80) == 0x80) ? "not " : "");
786 switch ((can) & 0x3) {
787 case 0:
788 printf ("CAN Controller is on address 0x1000..0x10FF\n");
789 break;
790 case 1:
791 printf ("CAN Controller is on address 0x8000..0x80FF\n");
792 break;
793 case 2:
794 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
795 break;
796 case 3:
797 printf ("CAN Controller is disabled\n");
798 break;
799 }
800 switch ((can >> 2) & 0x3) {
801 case 0:
802 printf ("CAN Controller Reset is ISA Reset\n");
803 break;
804 case 1:
805 printf ("CAN Controller Reset is ISA Reset and POS State\n");
806 break;
807 case 2:
808 case 3:
809 printf ("CAN Controller is in reset\n");
810 break;
811 }
812 if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
813 printf ("CAN Interrupt is disabled\n");
814 else
815 printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
816 switch (serpwr & 0x3) {
817 case 0:
818 printf ("SER0 Drivers are enabled\n");
819 break;
820 case 1:
821 printf ("SER0 Drivers are disabled in the POS state\n");
822 break;
823 case 2:
824 case 3:
825 printf ("SER0 Drivers are disabled\n");
826 break;
827 }
828 switch ((serpwr >> 2) & 0x3) {
829 case 0:
830 printf ("SER1 Drivers are enabled\n");
831 break;
832 case 1:
833 printf ("SER1 Drivers are disabled in the POS state\n");
834 break;
835 case 2:
836 case 3:
837 printf ("SER1 Drivers are disabled\n");
838 break;
839 }
840 switch (compwr & 0x3) {
841 case 0:
842 printf ("COM1 Drivers are enabled\n");
843 break;
844 case 1:
845 printf ("COM1 Drivers are disabled in the POS state\n");
846 break;
847 case 2:
848 case 3:
849 printf ("COM1 Drivers are disabled\n");
850 break;
851 }
852 switch ((compwr >> 2) & 0x3) {
853 case 0:
854 printf ("COM2 Drivers are enabled\n");
855 break;
856 case 1:
857 printf ("COM2 Drivers are disabled in the POS state\n");
858 break;
859 case 2:
860 case 3:
861 printf ("COM2 Drivers are disabled\n");
862 break;
863 }
864 switch ((nicvga) & 0x3) {
865 case 0:
866 printf ("PHY is running\n");
867 break;
868 case 1:
869 printf ("PHY is in Power save mode in POS state\n");
870 break;
871 case 2:
872 case 3:
873 printf ("PHY is in Power save mode\n");
874 break;
875 }
876 switch ((nicvga >> 2) & 0x3) {
877 case 0:
878 printf ("VGA is running\n");
879 break;
880 case 1:
881 printf ("VGA is in Power save mode in POS state\n");
882 break;
883 case 2:
884 case 3:
885 printf ("VGA is in Power save mode\n");
886 break;
887 }
888 printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
889 printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
890 printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
891 (nicvga >> 7) & 0x1);
892 switch ((scsirst) & 0x3) {
893 case 0:
894 printf ("SCSI Controller is running\n");
895 break;
896 case 1:
897 printf ("SCSI Controller is in Power save mode in POS state\n");
898 break;
899 case 2:
900 case 3:
901 printf ("SCSI Controller is in Power save mode\n");
902 break;
903 }
904 printf ("SCSI termination is %s\n",
905 ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
906 printf ("SCSI Controller is %sreseted\n",
907 ((scsirst & 0x10) == 0x10) ? "" : "not ");
908 printf ("IDE disks are %sreseted\n",
909 ((scsirst & 0x20) == 0x20) ? "" : "not ");
910 printf ("ISA Bus is %sreseted\n",
911 ((scsirst & 0x40) == 0x40) ? "" : "not ");
912 printf ("Super IO is %sreseted\n",
913 ((scsirst & 0x80) == 0x80) ? "" : "not ");
914}
915
916void user_led0 (unsigned char on)
917{
918 if (on == TRUE)
919 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
920 else
921 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
922}
923
924void user_led1 (unsigned char on)
925{
926 if (on == TRUE)
927 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
928 else
929 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
930}
931
932void ide_set_reset (int idereset)
933{
934 /* if reset = 1 IDE reset will be asserted */
935 unsigned char resreg;
936
937 resreg = in8 (PLD_SCSI_RST_REG);
938 if (idereset == 1)
939 resreg |= 0x20;
940 else {
941 udelay(10000);
942 resreg &= 0xdf;
943 }
944 out8 (PLD_SCSI_RST_REG, resreg);
945}
946
947