Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7d436078fe48d020eaee9416b5d4cd342dd106ab / . / board / freescale / t1040qds / tlb.c
blob: 412c591f1ca344139a8780fb0e13646fea7ec028 [file] [log] [blame]
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530[diff] [blame^]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/mmu.h>
9
10struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
14 MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 0, 0, BOOKE_PAGESZ_4K, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
26 MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
28
29 /* TLB 1 */
30 /* *I*** - Covers boot page */
31#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
32 /*
33 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
34 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
35 */
36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
37 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
38 0, 0, BOOKE_PAGESZ_256K, 1),
39#else
40 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42 0, 0, BOOKE_PAGESZ_4K, 1),
43#endif
44
45 /* *I*G* - CCSRBAR */
46 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
47 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
48 0, 1, BOOKE_PAGESZ_16M, 1),
49
50 /* *I*G* - Flash, localbus */
51 /* This will be changed to *I*G* after relocation to RAM. */
52 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
53 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
54 0, 2, BOOKE_PAGESZ_256M, 1),
55
56 /* *I*G* - PCI */
57 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 3, BOOKE_PAGESZ_1G, 1),
60
61 /* *I*G* - PCI I/O */
62 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 0, 4, BOOKE_PAGESZ_256K, 1),
65
66 /* Bman/Qman */
67#ifdef CONFIG_SYS_BMAN_MEM_PHYS
68 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
69 MAS3_SX|MAS3_SW|MAS3_SR, 0,
70 0, 5, BOOKE_PAGESZ_16M, 1),
71 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
72 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 0, 6, BOOKE_PAGESZ_16M, 1),
75#endif
76#ifdef CONFIG_SYS_QMAN_MEM_PHYS
77 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
78 MAS3_SX|MAS3_SW|MAS3_SR, 0,
79 0, 7, BOOKE_PAGESZ_16M, 1),
80 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
81 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, 8, BOOKE_PAGESZ_16M, 1),
84#endif
85#ifdef CONFIG_SYS_DCSRBAR_PHYS
86 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
88 0, 9, BOOKE_PAGESZ_4M, 1),
89#endif
90#ifdef CONFIG_SYS_NAND_BASE
91 /*
92 * *I*G - NAND
93 * entry 14 and 15 has been used hard coded, they will be disabled
94 * in cpu_init_f, so we use entry 16 for nand.
95 */
96 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
97 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
98 0, 10, BOOKE_PAGESZ_64K, 1),
99#endif
100#ifdef QIXIS_BASE
101 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
102 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
103 0, 11, BOOKE_PAGESZ_4K, 1),
104#endif
105
106};
107
108int num_tlb_entries = ARRAY_SIZE(tlb_table);