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maxims@google.com14e4b142017-01-18 13:44:56 -08001/*
2 * This device tree is copied from
maxims@google.com17c5fb12017-04-17 12:00:20 -07003 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
maxims@google.com14e4b142017-01-18 13:44:56 -08004 */
5#include "skeleton.dtsi"
6
7/ {
8 model = "Aspeed BMC";
9 compatible = "aspeed,ast2500";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&vic>;
13
Cédric Le Goater6bdccc32018-10-29 07:06:39 +010014 aliases {
15 i2c0 = &i2c0;
16 i2c1 = &i2c1;
17 i2c2 = &i2c2;
18 i2c3 = &i2c3;
19 i2c4 = &i2c4;
20 i2c5 = &i2c5;
21 i2c6 = &i2c6;
22 i2c7 = &i2c7;
23 i2c8 = &i2c8;
24 i2c9 = &i2c9;
25 i2c10 = &i2c10;
26 i2c11 = &i2c11;
27 i2c12 = &i2c12;
28 i2c13 = &i2c13;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &vuart;
35 };
36
maxims@google.com14e4b142017-01-18 13:44:56 -080037 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu@0 {
42 compatible = "arm,arm1176jzf-s";
43 device_type = "cpu";
44 reg = <0>;
45 };
46 };
47
Cédric Le Goater6bdccc32018-10-29 07:06:39 +010048 memory@80000000 {
49 device_type = "memory";
50 reg = <0x80000000 0>;
51 };
52
maxims@google.com14e4b142017-01-18 13:44:56 -080053 ahb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
Cédric Le Goater6bdccc32018-10-29 07:06:39 +010059 fmc: flash-controller@1e620000 {
60 reg = < 0x1e620000 0xc4
61 0x20000000 0x10000000 >;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 compatible = "aspeed,ast2500-fmc";
65 status = "disabled";
66 interrupts = <19>;
67 flash@0 {
68 reg = < 0 >;
69 compatible = "jedec,spi-nor";
70 status = "disabled";
71 };
72 flash@1 {
73 reg = < 1 >;
74 compatible = "jedec,spi-nor";
75 status = "disabled";
76 };
77 flash@2 {
78 reg = < 2 >;
79 compatible = "jedec,spi-nor";
80 status = "disabled";
81 };
82 };
83
84 spi1: flash-controller@1e630000 {
85 reg = < 0x1e630000 0xc4
86 0x30000000 0x08000000 >;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "aspeed,ast2500-spi";
90 status = "disabled";
91 flash@0 {
92 reg = < 0 >;
93 compatible = "jedec,spi-nor";
94 status = "disabled";
95 };
96 flash@1 {
97 reg = < 1 >;
98 compatible = "jedec,spi-nor";
99 status = "disabled";
100 };
101 };
102
103 spi2: flash-controller@1e631000 {
104 reg = < 0x1e631000 0xc4
105 0x38000000 0x08000000 >;
106 #address-cells = <1>;
107 #size-cells = <0>;
108 compatible = "aspeed,ast2500-spi";
109 status = "disabled";
110 flash@0 {
111 reg = < 0 >;
112 compatible = "jedec,spi-nor";
113 status = "disabled";
114 };
115 flash@1 {
116 reg = < 1 >;
117 compatible = "jedec,spi-nor";
118 status = "disabled";
119 };
120 };
121
maxims@google.com14e4b142017-01-18 13:44:56 -0800122 vic: interrupt-controller@1e6c0080 {
123 compatible = "aspeed,ast2400-vic";
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 valid-sources = <0xfefff7ff 0x0807ffff>;
127 reg = <0x1e6c0080 0x80>;
128 };
129
maxims@google.com17c5fb12017-04-17 12:00:20 -0700130 mac0: ethernet@1e660000 {
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100131 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
maxims@google.com17c5fb12017-04-17 12:00:20 -0700132 reg = <0x1e660000 0x180>;
133 interrupts = <2>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700134 status = "disabled";
135 };
136
137 mac1: ethernet@1e680000 {
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100138 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
maxims@google.com17c5fb12017-04-17 12:00:20 -0700139 reg = <0x1e680000 0x180>;
140 interrupts = <3>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100141 status = "disabled";
142 };
143
144 ehci0: usb@1e6a1000 {
145 compatible = "aspeed,ast2500-ehci", "generic-ehci";
146 reg = <0x1e6a1000 0x100>;
147 interrupts = <5>;
148 status = "disabled";
149 };
150
151 ehci1: usb@1e6a3000 {
152 compatible = "aspeed,ast2500-ehci", "generic-ehci";
153 reg = <0x1e6a3000 0x100>;
154 interrupts = <13>;
155 status = "disabled";
156 };
157
158 uhci: usb@1e6b0000 {
159 compatible = "aspeed,ast2500-uhci", "generic-uhci";
160 reg = <0x1e6b0000 0x100>;
161 interrupts = <14>;
162 #ports = <2>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700163 status = "disabled";
164 };
165
maxims@google.com14e4b142017-01-18 13:44:56 -0800166 apb {
167 compatible = "simple-bus";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges;
171
maxims@google.com17c5fb12017-04-17 12:00:20 -0700172 syscon: syscon@1e6e2000 {
173 compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
174 reg = <0x1e6e2000 0x1a8>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100175 #clock-cells = <1>;
176 #reset-cells = <1>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700177
178 pinctrl: pinctrl {
179 compatible = "aspeed,g5-pinctrl";
180 aspeed,external-nodes = <&gfx &lhc>;
181
maxims@google.com17c5fb12017-04-17 12:00:20 -0700182 };
183 };
184
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100185 rng: hwrng@1e6e2078 {
186 compatible = "timeriomem_rng";
187 reg = <0x1e6e2078 0x4>;
188 period = <1>;
189 quality = <100>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800190 };
191
maxims@google.com17c5fb12017-04-17 12:00:20 -0700192 gfx: display@1e6e6000 {
193 compatible = "aspeed,ast2500-gfx", "syscon";
194 reg = <0x1e6e6000 0x1000>;
195 reg-io-width = <4>;
196 };
197
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100198 adc: adc@1e6e9000 {
199 compatible = "aspeed,ast2500-adc";
200 reg = <0x1e6e9000 0xb0>;
201 #io-channel-cells = <1>;
202 status = "disabled";
203 };
204
maxims@google.com14e4b142017-01-18 13:44:56 -0800205 sram@1e720000 {
206 compatible = "mmio-sram";
207 reg = <0x1e720000 0x9000>; // 36K
208 };
209
maxims@google.com17c5fb12017-04-17 12:00:20 -0700210 gpio: gpio@1e780000 {
211 #gpio-cells = <2>;
212 gpio-controller;
213 compatible = "aspeed,ast2500-gpio";
214 reg = <0x1e780000 0x1000>;
215 interrupts = <20>;
216 gpio-ranges = <&pinctrl 0 0 220>;
Andrew Jeffery7da87542022-02-16 10:26:57 +1030217 ngpios = <228>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700218 interrupt-controller;
219 };
220
maxims@google.com14e4b142017-01-18 13:44:56 -0800221 timer: timer@1e782000 {
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100222 /* This timer is a Faraday FTTMR010 derivative */
maxims@google.com14e4b142017-01-18 13:44:56 -0800223 compatible = "aspeed,ast2400-timer";
224 reg = <0x1e782000 0x90>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800225 };
226
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100227 uart1: serial@1e783000 {
228 compatible = "ns16550a";
229 reg = <0x1e783000 0x20>;
230 reg-shift = <2>;
231 interrupts = <9>;
232 no-loopback-test;
233 status = "disabled";
234 };
maxims@google.com17c5fb12017-04-17 12:00:20 -0700235
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100236 uart5: serial@1e784000 {
237 compatible = "ns16550a";
238 reg = <0x1e784000 0x20>;
239 reg-shift = <2>;
240 interrupts = <10>;
241 no-loopback-test;
242 status = "disabled";
243 };
244
245 wdt1: watchdog@1e785000 {
maxims@google.com14e4b142017-01-18 13:44:56 -0800246 compatible = "aspeed,wdt";
247 reg = <0x1e785000 0x1c>;
248 interrupts = <27>;
249 };
250
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100251 wdt2: watchdog@1e785020 {
maxims@google.com14e4b142017-01-18 13:44:56 -0800252 compatible = "aspeed,wdt";
253 reg = <0x1e785020 0x1c>;
254 interrupts = <27>;
255 status = "disabled";
256 };
257
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100258 wdt3: watchdog@1e785040 {
maxims@google.com14e4b142017-01-18 13:44:56 -0800259 compatible = "aspeed,wdt";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100260 reg = <0x1e785040 0x1c>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800261 status = "disabled";
262 };
263
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100264 pwm_tacho: pwm-tacho-controller@1e786000 {
265 compatible = "aspeed,ast2500-pwm-tacho";
266 #address-cells = <1>;
267 #size-cells = <0>;
268 reg = <0x1e786000 0x1000>;
269 status = "disabled";
270 };
271
272 vuart: serial@1e787000 {
273 compatible = "aspeed,ast2500-vuart";
274 reg = <0x1e787000 0x40>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800275 reg-shift = <2>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100276 interrupts = <8>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800277 no-loopback-test;
278 status = "disabled";
279 };
280
maxims@google.com17c5fb12017-04-17 12:00:20 -0700281 lpc: lpc@1e789000 {
282 compatible = "aspeed,ast2500-lpc", "simple-mfd";
283 reg = <0x1e789000 0x1000>;
284
285 #address-cells = <1>;
286 #size-cells = <1>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100287 ranges = <0x0 0x1e789000 0x1000>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700288
289 lpc_bmc: lpc-bmc@0 {
290 compatible = "aspeed,ast2500-lpc-bmc";
291 reg = <0x0 0x80>;
292 };
293
294 lpc_host: lpc-host@80 {
295 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
296 reg = <0x80 0x1e0>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100297 reg-io-width = <4>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700298
299 #address-cells = <1>;
300 #size-cells = <1>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100301 ranges = <0x0 0x80 0x1e0>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700302
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100303 lpc_ctrl: lpc-ctrl@0 {
304 compatible = "aspeed,ast2500-lpc-ctrl";
305 reg = <0x0 0x80>;
306 status = "disabled";
307 };
308
309 lpc_snoop: lpc-snoop@0 {
310 compatible = "aspeed,ast2500-lpc-snoop";
311 reg = <0x0 0x80>;
312 interrupts = <8>;
313 status = "disabled";
314 };
maxims@google.com17c5fb12017-04-17 12:00:20 -0700315
316 lhc: lhc@20 {
317 compatible = "aspeed,ast2500-lhc";
318 reg = <0x20 0x24 0x48 0x8>;
319 };
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100320
321 lpc_reset: reset-controller@18 {
322 compatible = "aspeed,ast2500-lpc-reset";
323 reg = <0x18 0x4>;
324 #reset-cells = <1>;
325 };
326
327 ibt: ibt@c0 {
328 compatible = "aspeed,ast2500-ibt-bmc";
329 reg = <0xc0 0x18>;
330 interrupts = <8>;
331 status = "disabled";
332 };
maxims@google.com17c5fb12017-04-17 12:00:20 -0700333 };
334 };
335
maxims@google.com14e4b142017-01-18 13:44:56 -0800336 uart2: serial@1e78d000 {
337 compatible = "ns16550a";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100338 reg = <0x1e78d000 0x20>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800339 reg-shift = <2>;
340 interrupts = <32>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800341 no-loopback-test;
342 status = "disabled";
343 };
344
345 uart3: serial@1e78e000 {
346 compatible = "ns16550a";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100347 reg = <0x1e78e000 0x20>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800348 reg-shift = <2>;
349 interrupts = <33>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800350 no-loopback-test;
351 status = "disabled";
352 };
353
354 uart4: serial@1e78f000 {
355 compatible = "ns16550a";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100356 reg = <0x1e78f000 0x20>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800357 reg-shift = <2>;
358 interrupts = <34>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800359 no-loopback-test;
360 status = "disabled";
361 };
362
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100363 i2c: i2c@1e78a000 {
364 compatible = "simple-bus";
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges = <0 0x1e78a000 0x1000>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800368 };
369 };
370 };
371};
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100372
373&i2c {
374 i2c_ic: interrupt-controller@0 {
375 #interrupt-cells = <1>;
376 compatible = "aspeed,ast2500-i2c-ic";
377 reg = <0x0 0x40>;
378 interrupts = <12>;
379 interrupt-controller;
380 };
381
382 i2c0: i2c-bus@40 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 #interrupt-cells = <1>;
386
387 reg = <0x40 0x40>;
388 compatible = "aspeed,ast2500-i2c-bus";
389 bus-frequency = <100000>;
390 interrupts = <0>;
391 interrupt-parent = <&i2c_ic>;
392 status = "disabled";
393 /* Does not need pinctrl properties */
394 };
395
396 i2c1: i2c-bus@80 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 #interrupt-cells = <1>;
400
401 reg = <0x80 0x40>;
402 compatible = "aspeed,ast2500-i2c-bus";
403 bus-frequency = <100000>;
404 interrupts = <1>;
405 interrupt-parent = <&i2c_ic>;
406 status = "disabled";
407 /* Does not need pinctrl properties */
408 };
409
410 i2c2: i2c-bus@c0 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 #interrupt-cells = <1>;
414
415 reg = <0xc0 0x40>;
416 compatible = "aspeed,ast2500-i2c-bus";
417 bus-frequency = <100000>;
418 interrupts = <2>;
419 interrupt-parent = <&i2c_ic>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_i2c3_default>;
422 status = "disabled";
423 };
424
425 i2c3: i2c-bus@100 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 #interrupt-cells = <1>;
429
430 reg = <0x100 0x40>;
431 compatible = "aspeed,ast2500-i2c-bus";
432 bus-frequency = <100000>;
433 interrupts = <3>;
434 interrupt-parent = <&i2c_ic>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_i2c4_default>;
437 status = "disabled";
438 };
439
440 i2c4: i2c-bus@140 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 #interrupt-cells = <1>;
444
445 reg = <0x140 0x40>;
446 compatible = "aspeed,ast2500-i2c-bus";
447 bus-frequency = <100000>;
448 interrupts = <4>;
449 interrupt-parent = <&i2c_ic>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&pinctrl_i2c5_default>;
452 status = "disabled";
453 };
454
455 i2c5: i2c-bus@180 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 #interrupt-cells = <1>;
459
460 reg = <0x180 0x40>;
461 compatible = "aspeed,ast2500-i2c-bus";
462 bus-frequency = <100000>;
463 interrupts = <5>;
464 interrupt-parent = <&i2c_ic>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_i2c6_default>;
467 status = "disabled";
468 };
469
470 i2c6: i2c-bus@1c0 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 #interrupt-cells = <1>;
474
475 reg = <0x1c0 0x40>;
476 compatible = "aspeed,ast2500-i2c-bus";
477 bus-frequency = <100000>;
478 interrupts = <6>;
479 interrupt-parent = <&i2c_ic>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_i2c7_default>;
482 status = "disabled";
483 };
484
485 i2c7: i2c-bus@300 {
486 #address-cells = <1>;
487 #size-cells = <0>;
488 #interrupt-cells = <1>;
489
490 reg = <0x300 0x40>;
491 compatible = "aspeed,ast2500-i2c-bus";
492 bus-frequency = <100000>;
493 interrupts = <7>;
494 interrupt-parent = <&i2c_ic>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_i2c8_default>;
497 status = "disabled";
498 };
499
500 i2c8: i2c-bus@340 {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 #interrupt-cells = <1>;
504
505 reg = <0x340 0x40>;
506 compatible = "aspeed,ast2500-i2c-bus";
507 bus-frequency = <100000>;
508 interrupts = <8>;
509 interrupt-parent = <&i2c_ic>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_i2c9_default>;
512 status = "disabled";
513 };
514
515 i2c9: i2c-bus@380 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 #interrupt-cells = <1>;
519
520 reg = <0x380 0x40>;
521 compatible = "aspeed,ast2500-i2c-bus";
522 bus-frequency = <100000>;
523 interrupts = <9>;
524 interrupt-parent = <&i2c_ic>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_i2c10_default>;
527 status = "disabled";
528 };
529
530 i2c10: i2c-bus@3c0 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 #interrupt-cells = <1>;
534
535 reg = <0x3c0 0x40>;
536 compatible = "aspeed,ast2500-i2c-bus";
537 bus-frequency = <100000>;
538 interrupts = <10>;
539 interrupt-parent = <&i2c_ic>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_i2c11_default>;
542 status = "disabled";
543 };
544
545 i2c11: i2c-bus@400 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 #interrupt-cells = <1>;
549
550 reg = <0x400 0x40>;
551 compatible = "aspeed,ast2500-i2c-bus";
552 bus-frequency = <100000>;
553 interrupts = <11>;
554 interrupt-parent = <&i2c_ic>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_i2c12_default>;
557 status = "disabled";
558 };
559
560 i2c12: i2c-bus@440 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 #interrupt-cells = <1>;
564
565 reg = <0x440 0x40>;
566 compatible = "aspeed,ast2500-i2c-bus";
567 bus-frequency = <100000>;
568 interrupts = <12>;
569 interrupt-parent = <&i2c_ic>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_i2c13_default>;
572 status = "disabled";
573 };
574
575 i2c13: i2c-bus@480 {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 #interrupt-cells = <1>;
579
580 reg = <0x480 0x40>;
581 compatible = "aspeed,ast2500-i2c-bus";
582 bus-frequency = <100000>;
583 interrupts = <13>;
584 interrupt-parent = <&i2c_ic>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_i2c14_default>;
587 status = "disabled";
588 };
589};
590
591&pinctrl {
592 pinctrl_acpi_default: acpi_default {
593 function = "ACPI";
594 groups = "ACPI";
595 };
596
597 pinctrl_adc0_default: adc0_default {
598 function = "ADC0";
599 groups = "ADC0";
600 };
601
602 pinctrl_adc1_default: adc1_default {
603 function = "ADC1";
604 groups = "ADC1";
605 };
606
607 pinctrl_adc10_default: adc10_default {
608 function = "ADC10";
609 groups = "ADC10";
610 };
611
612 pinctrl_adc11_default: adc11_default {
613 function = "ADC11";
614 groups = "ADC11";
615 };
616
617 pinctrl_adc12_default: adc12_default {
618 function = "ADC12";
619 groups = "ADC12";
620 };
621
622 pinctrl_adc13_default: adc13_default {
623 function = "ADC13";
624 groups = "ADC13";
625 };
626
627 pinctrl_adc14_default: adc14_default {
628 function = "ADC14";
629 groups = "ADC14";
630 };
631
632 pinctrl_adc15_default: adc15_default {
633 function = "ADC15";
634 groups = "ADC15";
635 };
636
637 pinctrl_adc2_default: adc2_default {
638 function = "ADC2";
639 groups = "ADC2";
640 };
641
642 pinctrl_adc3_default: adc3_default {
643 function = "ADC3";
644 groups = "ADC3";
645 };
646
647 pinctrl_adc4_default: adc4_default {
648 function = "ADC4";
649 groups = "ADC4";
650 };
651
652 pinctrl_adc5_default: adc5_default {
653 function = "ADC5";
654 groups = "ADC5";
655 };
656
657 pinctrl_adc6_default: adc6_default {
658 function = "ADC6";
659 groups = "ADC6";
660 };
661
662 pinctrl_adc7_default: adc7_default {
663 function = "ADC7";
664 groups = "ADC7";
665 };
666
667 pinctrl_adc8_default: adc8_default {
668 function = "ADC8";
669 groups = "ADC8";
670 };
671
672 pinctrl_adc9_default: adc9_default {
673 function = "ADC9";
674 groups = "ADC9";
675 };
676
677 pinctrl_bmcint_default: bmcint_default {
678 function = "BMCINT";
679 groups = "BMCINT";
680 };
681
682 pinctrl_ddcclk_default: ddcclk_default {
683 function = "DDCCLK";
684 groups = "DDCCLK";
685 };
686
687 pinctrl_ddcdat_default: ddcdat_default {
688 function = "DDCDAT";
689 groups = "DDCDAT";
690 };
691
692 pinctrl_espi_default: espi_default {
693 function = "ESPI";
694 groups = "ESPI";
695 };
696
697 pinctrl_fwspics1_default: fwspics1_default {
698 function = "FWSPICS1";
699 groups = "FWSPICS1";
700 };
701
702 pinctrl_fwspics2_default: fwspics2_default {
703 function = "FWSPICS2";
704 groups = "FWSPICS2";
705 };
706
707 pinctrl_gpid0_default: gpid0_default {
708 function = "GPID0";
709 groups = "GPID0";
710 };
711
712 pinctrl_gpid2_default: gpid2_default {
713 function = "GPID2";
714 groups = "GPID2";
715 };
716
717 pinctrl_gpid4_default: gpid4_default {
718 function = "GPID4";
719 groups = "GPID4";
720 };
721
722 pinctrl_gpid6_default: gpid6_default {
723 function = "GPID6";
724 groups = "GPID6";
725 };
726
727 pinctrl_gpie0_default: gpie0_default {
728 function = "GPIE0";
729 groups = "GPIE0";
730 };
731
732 pinctrl_gpie2_default: gpie2_default {
733 function = "GPIE2";
734 groups = "GPIE2";
735 };
736
737 pinctrl_gpie4_default: gpie4_default {
738 function = "GPIE4";
739 groups = "GPIE4";
740 };
741
742 pinctrl_gpie6_default: gpie6_default {
743 function = "GPIE6";
744 groups = "GPIE6";
745 };
746
747 pinctrl_i2c10_default: i2c10_default {
748 function = "I2C10";
749 groups = "I2C10";
750 };
751
752 pinctrl_i2c11_default: i2c11_default {
753 function = "I2C11";
754 groups = "I2C11";
755 };
756
757 pinctrl_i2c12_default: i2c12_default {
758 function = "I2C12";
759 groups = "I2C12";
760 };
761
762 pinctrl_i2c13_default: i2c13_default {
763 function = "I2C13";
764 groups = "I2C13";
765 };
766
767 pinctrl_i2c14_default: i2c14_default {
768 function = "I2C14";
769 groups = "I2C14";
770 };
771
772 pinctrl_i2c3_default: i2c3_default {
773 function = "I2C3";
774 groups = "I2C3";
775 };
776
777 pinctrl_i2c4_default: i2c4_default {
778 function = "I2C4";
779 groups = "I2C4";
780 };
781
782 pinctrl_i2c5_default: i2c5_default {
783 function = "I2C5";
784 groups = "I2C5";
785 };
786
787 pinctrl_i2c6_default: i2c6_default {
788 function = "I2C6";
789 groups = "I2C6";
790 };
791
792 pinctrl_i2c7_default: i2c7_default {
793 function = "I2C7";
794 groups = "I2C7";
795 };
796
797 pinctrl_i2c8_default: i2c8_default {
798 function = "I2C8";
799 groups = "I2C8";
800 };
801
802 pinctrl_i2c9_default: i2c9_default {
803 function = "I2C9";
804 groups = "I2C9";
805 };
806
807 pinctrl_lad0_default: lad0_default {
808 function = "LAD0";
809 groups = "LAD0";
810 };
811
812 pinctrl_lad1_default: lad1_default {
813 function = "LAD1";
814 groups = "LAD1";
815 };
816
817 pinctrl_lad2_default: lad2_default {
818 function = "LAD2";
819 groups = "LAD2";
820 };
821
822 pinctrl_lad3_default: lad3_default {
823 function = "LAD3";
824 groups = "LAD3";
825 };
826
827 pinctrl_lclk_default: lclk_default {
828 function = "LCLK";
829 groups = "LCLK";
830 };
831
832 pinctrl_lframe_default: lframe_default {
833 function = "LFRAME";
834 groups = "LFRAME";
835 };
836
837 pinctrl_lpchc_default: lpchc_default {
838 function = "LPCHC";
839 groups = "LPCHC";
840 };
841
842 pinctrl_lpcpd_default: lpcpd_default {
843 function = "LPCPD";
844 groups = "LPCPD";
845 };
846
847 pinctrl_lpcplus_default: lpcplus_default {
848 function = "LPCPLUS";
849 groups = "LPCPLUS";
850 };
851
852 pinctrl_lpcpme_default: lpcpme_default {
853 function = "LPCPME";
854 groups = "LPCPME";
855 };
856
857 pinctrl_lpcrst_default: lpcrst_default {
858 function = "LPCRST";
859 groups = "LPCRST";
860 };
861
862 pinctrl_lpcsmi_default: lpcsmi_default {
863 function = "LPCSMI";
864 groups = "LPCSMI";
865 };
866
867 pinctrl_lsirq_default: lsirq_default {
868 function = "LSIRQ";
869 groups = "LSIRQ";
870 };
871
872 pinctrl_mac1link_default: mac1link_default {
873 function = "MAC1LINK";
874 groups = "MAC1LINK";
875 };
876
877 pinctrl_mac2link_default: mac2link_default {
878 function = "MAC2LINK";
879 groups = "MAC2LINK";
880 };
881
882 pinctrl_mdio1_default: mdio1_default {
883 function = "MDIO1";
884 groups = "MDIO1";
885 };
886
887 pinctrl_mdio2_default: mdio2_default {
888 function = "MDIO2";
889 groups = "MDIO2";
890 };
891
892 pinctrl_ncts1_default: ncts1_default {
893 function = "NCTS1";
894 groups = "NCTS1";
895 };
896
897 pinctrl_ncts2_default: ncts2_default {
898 function = "NCTS2";
899 groups = "NCTS2";
900 };
901
902 pinctrl_ncts3_default: ncts3_default {
903 function = "NCTS3";
904 groups = "NCTS3";
905 };
906
907 pinctrl_ncts4_default: ncts4_default {
908 function = "NCTS4";
909 groups = "NCTS4";
910 };
911
912 pinctrl_ndcd1_default: ndcd1_default {
913 function = "NDCD1";
914 groups = "NDCD1";
915 };
916
917 pinctrl_ndcd2_default: ndcd2_default {
918 function = "NDCD2";
919 groups = "NDCD2";
920 };
921
922 pinctrl_ndcd3_default: ndcd3_default {
923 function = "NDCD3";
924 groups = "NDCD3";
925 };
926
927 pinctrl_ndcd4_default: ndcd4_default {
928 function = "NDCD4";
929 groups = "NDCD4";
930 };
931
932 pinctrl_ndsr1_default: ndsr1_default {
933 function = "NDSR1";
934 groups = "NDSR1";
935 };
936
937 pinctrl_ndsr2_default: ndsr2_default {
938 function = "NDSR2";
939 groups = "NDSR2";
940 };
941
942 pinctrl_ndsr3_default: ndsr3_default {
943 function = "NDSR3";
944 groups = "NDSR3";
945 };
946
947 pinctrl_ndsr4_default: ndsr4_default {
948 function = "NDSR4";
949 groups = "NDSR4";
950 };
951
952 pinctrl_ndtr1_default: ndtr1_default {
953 function = "NDTR1";
954 groups = "NDTR1";
955 };
956
957 pinctrl_ndtr2_default: ndtr2_default {
958 function = "NDTR2";
959 groups = "NDTR2";
960 };
961
962 pinctrl_ndtr3_default: ndtr3_default {
963 function = "NDTR3";
964 groups = "NDTR3";
965 };
966
967 pinctrl_ndtr4_default: ndtr4_default {
968 function = "NDTR4";
969 groups = "NDTR4";
970 };
971
972 pinctrl_nri1_default: nri1_default {
973 function = "NRI1";
974 groups = "NRI1";
975 };
976
977 pinctrl_nri2_default: nri2_default {
978 function = "NRI2";
979 groups = "NRI2";
980 };
981
982 pinctrl_nri3_default: nri3_default {
983 function = "NRI3";
984 groups = "NRI3";
985 };
986
987 pinctrl_nri4_default: nri4_default {
988 function = "NRI4";
989 groups = "NRI4";
990 };
991
992 pinctrl_nrts1_default: nrts1_default {
993 function = "NRTS1";
994 groups = "NRTS1";
995 };
996
997 pinctrl_nrts2_default: nrts2_default {
998 function = "NRTS2";
999 groups = "NRTS2";
1000 };
1001
1002 pinctrl_nrts3_default: nrts3_default {
1003 function = "NRTS3";
1004 groups = "NRTS3";
1005 };
1006
1007 pinctrl_nrts4_default: nrts4_default {
1008 function = "NRTS4";
1009 groups = "NRTS4";
1010 };
1011
1012 pinctrl_oscclk_default: oscclk_default {
1013 function = "OSCCLK";
1014 groups = "OSCCLK";
1015 };
1016
1017 pinctrl_pewake_default: pewake_default {
1018 function = "PEWAKE";
1019 groups = "PEWAKE";
1020 };
1021
1022 pinctrl_pnor_default: pnor_default {
1023 function = "PNOR";
1024 groups = "PNOR";
1025 };
1026
1027 pinctrl_pwm0_default: pwm0_default {
1028 function = "PWM0";
1029 groups = "PWM0";
1030 };
1031
1032 pinctrl_pwm1_default: pwm1_default {
1033 function = "PWM1";
1034 groups = "PWM1";
1035 };
1036
1037 pinctrl_pwm2_default: pwm2_default {
1038 function = "PWM2";
1039 groups = "PWM2";
1040 };
1041
1042 pinctrl_pwm3_default: pwm3_default {
1043 function = "PWM3";
1044 groups = "PWM3";
1045 };
1046
1047 pinctrl_pwm4_default: pwm4_default {
1048 function = "PWM4";
1049 groups = "PWM4";
1050 };
1051
1052 pinctrl_pwm5_default: pwm5_default {
1053 function = "PWM5";
1054 groups = "PWM5";
1055 };
1056
1057 pinctrl_pwm6_default: pwm6_default {
1058 function = "PWM6";
1059 groups = "PWM6";
1060 };
1061
1062 pinctrl_pwm7_default: pwm7_default {
1063 function = "PWM7";
1064 groups = "PWM7";
1065 };
1066
1067 pinctrl_rgmii1_default: rgmii1_default {
1068 function = "RGMII1";
1069 groups = "RGMII1";
1070 };
1071
1072 pinctrl_rgmii2_default: rgmii2_default {
1073 function = "RGMII2";
1074 groups = "RGMII2";
1075 };
1076
1077 pinctrl_rmii1_default: rmii1_default {
1078 function = "RMII1";
1079 groups = "RMII1";
1080 };
1081
1082 pinctrl_rmii2_default: rmii2_default {
1083 function = "RMII2";
1084 groups = "RMII2";
1085 };
1086
1087 pinctrl_rxd1_default: rxd1_default {
1088 function = "RXD1";
1089 groups = "RXD1";
1090 };
1091
1092 pinctrl_rxd2_default: rxd2_default {
1093 function = "RXD2";
1094 groups = "RXD2";
1095 };
1096
1097 pinctrl_rxd3_default: rxd3_default {
1098 function = "RXD3";
1099 groups = "RXD3";
1100 };
1101
1102 pinctrl_rxd4_default: rxd4_default {
1103 function = "RXD4";
1104 groups = "RXD4";
1105 };
1106
1107 pinctrl_salt1_default: salt1_default {
1108 function = "SALT1";
1109 groups = "SALT1";
1110 };
1111
1112 pinctrl_salt10_default: salt10_default {
1113 function = "SALT10";
1114 groups = "SALT10";
1115 };
1116
1117 pinctrl_salt11_default: salt11_default {
1118 function = "SALT11";
1119 groups = "SALT11";
1120 };
1121
1122 pinctrl_salt12_default: salt12_default {
1123 function = "SALT12";
1124 groups = "SALT12";
1125 };
1126
1127 pinctrl_salt13_default: salt13_default {
1128 function = "SALT13";
1129 groups = "SALT13";
1130 };
1131
1132 pinctrl_salt14_default: salt14_default {
1133 function = "SALT14";
1134 groups = "SALT14";
1135 };
1136
1137 pinctrl_salt2_default: salt2_default {
1138 function = "SALT2";
1139 groups = "SALT2";
1140 };
1141
1142 pinctrl_salt3_default: salt3_default {
1143 function = "SALT3";
1144 groups = "SALT3";
1145 };
1146
1147 pinctrl_salt4_default: salt4_default {
1148 function = "SALT4";
1149 groups = "SALT4";
1150 };
1151
1152 pinctrl_salt5_default: salt5_default {
1153 function = "SALT5";
1154 groups = "SALT5";
1155 };
1156
1157 pinctrl_salt6_default: salt6_default {
1158 function = "SALT6";
1159 groups = "SALT6";
1160 };
1161
1162 pinctrl_salt7_default: salt7_default {
1163 function = "SALT7";
1164 groups = "SALT7";
1165 };
1166
1167 pinctrl_salt8_default: salt8_default {
1168 function = "SALT8";
1169 groups = "SALT8";
1170 };
1171
1172 pinctrl_salt9_default: salt9_default {
1173 function = "SALT9";
1174 groups = "SALT9";
1175 };
1176
1177 pinctrl_scl1_default: scl1_default {
1178 function = "SCL1";
1179 groups = "SCL1";
1180 };
1181
1182 pinctrl_scl2_default: scl2_default {
1183 function = "SCL2";
1184 groups = "SCL2";
1185 };
1186
1187 pinctrl_sd1_default: sd1_default {
1188 function = "SD1";
1189 groups = "SD1";
1190 };
1191
1192 pinctrl_sd2_default: sd2_default {
1193 function = "SD2";
1194 groups = "SD2";
1195 };
1196
1197 pinctrl_sda1_default: sda1_default {
1198 function = "SDA1";
1199 groups = "SDA1";
1200 };
1201
1202 pinctrl_sda2_default: sda2_default {
1203 function = "SDA2";
1204 groups = "SDA2";
1205 };
1206
1207 pinctrl_sgps1_default: sgps1_default {
1208 function = "SGPS1";
1209 groups = "SGPS1";
1210 };
1211
1212 pinctrl_sgps2_default: sgps2_default {
1213 function = "SGPS2";
1214 groups = "SGPS2";
1215 };
1216
1217 pinctrl_sioonctrl_default: sioonctrl_default {
1218 function = "SIOONCTRL";
1219 groups = "SIOONCTRL";
1220 };
1221
1222 pinctrl_siopbi_default: siopbi_default {
1223 function = "SIOPBI";
1224 groups = "SIOPBI";
1225 };
1226
1227 pinctrl_siopbo_default: siopbo_default {
1228 function = "SIOPBO";
1229 groups = "SIOPBO";
1230 };
1231
1232 pinctrl_siopwreq_default: siopwreq_default {
1233 function = "SIOPWREQ";
1234 groups = "SIOPWREQ";
1235 };
1236
1237 pinctrl_siopwrgd_default: siopwrgd_default {
1238 function = "SIOPWRGD";
1239 groups = "SIOPWRGD";
1240 };
1241
1242 pinctrl_sios3_default: sios3_default {
1243 function = "SIOS3";
1244 groups = "SIOS3";
1245 };
1246
1247 pinctrl_sios5_default: sios5_default {
1248 function = "SIOS5";
1249 groups = "SIOS5";
1250 };
1251
1252 pinctrl_siosci_default: siosci_default {
1253 function = "SIOSCI";
1254 groups = "SIOSCI";
1255 };
1256
1257 pinctrl_spi1_default: spi1_default {
1258 function = "SPI1";
1259 groups = "SPI1";
1260 };
1261
1262 pinctrl_spi1cs1_default: spi1cs1_default {
1263 function = "SPI1CS1";
1264 groups = "SPI1CS1";
1265 };
1266
1267 pinctrl_spi1debug_default: spi1debug_default {
1268 function = "SPI1DEBUG";
1269 groups = "SPI1DEBUG";
1270 };
1271
1272 pinctrl_spi1passthru_default: spi1passthru_default {
1273 function = "SPI1PASSTHRU";
1274 groups = "SPI1PASSTHRU";
1275 };
1276
1277 pinctrl_spi2ck_default: spi2ck_default {
1278 function = "SPI2CK";
1279 groups = "SPI2CK";
1280 };
1281
1282 pinctrl_spi2cs0_default: spi2cs0_default {
1283 function = "SPI2CS0";
1284 groups = "SPI2CS0";
1285 };
1286
1287 pinctrl_spi2cs1_default: spi2cs1_default {
1288 function = "SPI2CS1";
1289 groups = "SPI2CS1";
1290 };
1291
1292 pinctrl_spi2miso_default: spi2miso_default {
1293 function = "SPI2MISO";
1294 groups = "SPI2MISO";
1295 };
1296
1297 pinctrl_spi2mosi_default: spi2mosi_default {
1298 function = "SPI2MOSI";
1299 groups = "SPI2MOSI";
1300 };
1301
1302 pinctrl_timer3_default: timer3_default {
1303 function = "TIMER3";
1304 groups = "TIMER3";
1305 };
1306
1307 pinctrl_timer4_default: timer4_default {
1308 function = "TIMER4";
1309 groups = "TIMER4";
1310 };
1311
1312 pinctrl_timer5_default: timer5_default {
1313 function = "TIMER5";
1314 groups = "TIMER5";
1315 };
1316
1317 pinctrl_timer6_default: timer6_default {
1318 function = "TIMER6";
1319 groups = "TIMER6";
1320 };
1321
1322 pinctrl_timer7_default: timer7_default {
1323 function = "TIMER7";
1324 groups = "TIMER7";
1325 };
1326
1327 pinctrl_timer8_default: timer8_default {
1328 function = "TIMER8";
1329 groups = "TIMER8";
1330 };
1331
1332 pinctrl_txd1_default: txd1_default {
1333 function = "TXD1";
1334 groups = "TXD1";
1335 };
1336
1337 pinctrl_txd2_default: txd2_default {
1338 function = "TXD2";
1339 groups = "TXD2";
1340 };
1341
1342 pinctrl_txd3_default: txd3_default {
1343 function = "TXD3";
1344 groups = "TXD3";
1345 };
1346
1347 pinctrl_txd4_default: txd4_default {
1348 function = "TXD4";
1349 groups = "TXD4";
1350 };
1351
1352 pinctrl_uart6_default: uart6_default {
1353 function = "UART6";
1354 groups = "UART6";
1355 };
1356
1357 pinctrl_usbcki_default: usbcki_default {
1358 function = "USBCKI";
1359 groups = "USBCKI";
1360 };
1361
1362 pinctrl_usb2ah_default: usb2ah_default {
1363 function = "USB2AH";
1364 groups = "USB2AH";
1365 };
1366
1367 pinctrl_usb11bhid_default: usb11bhid_default {
1368 function = "USB11BHID";
1369 groups = "USB11BHID";
1370 };
1371
1372 pinctrl_usb2bh_default: usb2bh_default {
1373 function = "USB2BH";
1374 groups = "USB2BH";
1375 };
1376
1377 pinctrl_vgabiosrom_default: vgabiosrom_default {
1378 function = "VGABIOSROM";
1379 groups = "VGABIOSROM";
1380 };
1381
1382 pinctrl_vgahs_default: vgahs_default {
1383 function = "VGAHS";
1384 groups = "VGAHS";
1385 };
1386
1387 pinctrl_vgavs_default: vgavs_default {
1388 function = "VGAVS";
1389 groups = "VGAVS";
1390 };
1391
1392 pinctrl_vpi24_default: vpi24_default {
1393 function = "VPI24";
1394 groups = "VPI24";
1395 };
1396
1397 pinctrl_vpo_default: vpo_default {
1398 function = "VPO";
1399 groups = "VPO";
1400 };
1401
1402 pinctrl_wdtrst1_default: wdtrst1_default {
1403 function = "WDTRST1";
1404 groups = "WDTRST1";
1405 };
1406
1407 pinctrl_wdtrst2_default: wdtrst2_default {
1408 function = "WDTRST2";
1409 groups = "WDTRST2";
1410 };
1411};