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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * Copyright(c) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
5 */
6
7#ifndef __MPC85xx_H__
8#define __MPC85xx_H__
9
wdenk0ac6f8b2004-07-09 23:27:13 +000010#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
Rafal Jaworowski02032e82007-06-22 14:58:04 +020011#define _START_OFFSET EXC_OFF_SYS_RESET
wdenk42d1f032003-10-15 23:53:47 +000012
13#if defined(CONFIG_E500)
14#include <e500.h>
15#endif
16
wdenk0ac6f8b2004-07-09 23:27:13 +000017/*
18 * SCCR - System Clock Control Register, 9-8
wdenk42d1f032003-10-15 23:53:47 +000019 */
wdenk0ac6f8b2004-07-09 23:27:13 +000020#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
21#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
wdenk42d1f032003-10-15 23:53:47 +000022#define SCCR_DFBRG_SHIFT 0
23
wdenk0ac6f8b2004-07-09 23:27:13 +000024#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
25#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
26#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
27#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
wdenk42d1f032003-10-15 23:53:47 +000028
Wolfgang Denkca273812006-03-12 22:45:47 +010029/*
30 * Local Bus Controller - memory controller registers
31 */
32#define BRx_V 0x00000001 /* Bank Valid */
33#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
34#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */
35#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
36#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
37#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
38#define BRx_PS_8 0x00000800 /* 8 bit port size */
39#define BRx_PS_32 0x00001800 /* 32 bit port size */
40#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
41
42#define ORxG_EAD 0x00000001 /* External addr latch delay */
43#define ORxG_EHTR 0x00000002 /* Extended hold time on read */
44#define ORxG_TRLX 0x00000004 /* Timing relaxed */
45#define ORxG_SETA 0x00000008 /* External address termination */
46#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
47#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
48#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */
49#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
50#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
51
52#define ORxU_BI 0x00000100 /* Burst Inhibit */
53#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
54
55#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
56#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
57#define MxMR_OP_WARR 0x10000000 /* Write to Array */
58#define MxMR_BSEL 0x80000000 /* Bus Select */
59
60/* helpers to convert values into an OR address mask (GPCM mode) */
61#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
62#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
63
wdenk42d1f032003-10-15 23:53:47 +000064#endif /* __MPC85xx_H__ */