blob: 7c272334aa52a09a7bc449b77f8a3e3f2931edc3 [file] [log] [blame]
Lunsheng Wangb0e32942005-07-29 10:20:29 -05001/*
2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
Lunsheng Wangb0e32942005-07-29 10:20:29 -050026#include <common.h>
Ben Warren8ca0b3f2008-08-31 10:45:44 -070027#include <netdev.h>
Lunsheng Wangb0e32942005-07-29 10:20:29 -050028#include <asm/processor.h>
Kumar Gala9658bec2008-08-26 23:52:32 -050029#include <asm/mmu.h>
Lunsheng Wangb0e32942005-07-29 10:20:29 -050030#include <asm/immap_85xx.h>
Kumar Gala9658bec2008-08-26 23:52:32 -050031#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060032#include <spd_sdram.h>
Lunsheng Wangb0e32942005-07-29 10:20:29 -050033
34long int fixed_sdram (void);
35
Lunsheng Wangb0e32942005-07-29 10:20:29 -050036int board_pre_init (void)
37{
38#if defined(CONFIG_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050040
41 pci->peer &= 0xffffffdf; /* disable master abort */
42#endif
43 return 0;
44}
45
46int checkboard (void)
47{
48 sys_info_t sysinfo;
49
50 get_sys_info (&sysinfo);
51
52 printf ("Board: Freescale MPC8540EVAL Board\n");
Kumar Gala9cda4f12009-01-28 08:31:10 -060053 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050054 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
55 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
57 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
Jon Loeligerde1d0a62005-08-01 13:20:47 -050058 printf ("\tLBC: %lu MHz\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059 sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
Lunsheng Wangb0e32942005-07-29 10:20:29 -050060 } else {
61 printf("\tLBC: unknown\n");
62 }
63 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
64 return (0);
65}
66
Becky Bruce9973e3c2008-06-09 16:03:40 -050067phys_size_t initdram (int board_type)
Lunsheng Wangb0e32942005-07-29 10:20:29 -050068{
69 long dram_size = 0;
Jon Loeligera30a5492008-03-04 10:03:03 -060070
Lunsheng Wangb0e32942005-07-29 10:20:29 -050071#if !defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050073 sys_info_t sysinfo;
74 uint temp_lbcdll = 0;
75#endif
76#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050078#endif
79
80#if defined(CONFIG_DDR_DLL)
81 uint temp_ddrdll = 0;
82
83 /* Work around to stabilize DDR DLL */
84 temp_ddrdll = gur->ddrdllcr;
85 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
86 asm("sync;isync;msync");
87#endif
88
89#if defined(CONFIG_SPD_EEPROM)
Kumar Gala9658bec2008-08-26 23:52:32 -050090 dram_size = fsl_ddr_sdram();
91 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
92 dram_size *= 0x100000;
Lunsheng Wangb0e32942005-07-29 10:20:29 -050093#else
94 dram_size = fixed_sdram ();
95#endif
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#if defined(CONFIG_SYS_RAMBOOT)
Lunsheng Wangb0e32942005-07-29 10:20:29 -050098 return dram_size;
99#endif
100
101#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
102 get_sys_info(&sysinfo);
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200103 /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
Trent Piephoa5d212a2008-12-03 15:16:34 -0800104 if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105 lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500106 } else {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500108 udelay(200);
109 temp_lbcdll = gur->lbcdllcr;
110 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
111 asm("sync;isync;msync");
112 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
114 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
115 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
116 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500117 asm("sync");
118 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500120 asm("sync");
121 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500123 asm("sync");
124 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500126 asm("sync");
127 * (ulong *)0 = 0x000000ff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500129 asm("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500131 asm("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500133 asm("sync");
134#endif
135
136#if defined(CONFIG_DDR_ECC)
137 {
138 /* Initialize all of memory for ECC, then
139 * enable errors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Peter Tyser79f43332009-06-30 17:15:47 -0500141
Peter Tyser0d595f72009-06-30 17:15:48 -0500142 dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500143
144 /* Enable errors for ECC */
145 ddr->err_disable = 0x00000000;
146 asm("sync;isync;msync");
147 }
148#endif
149
150 return dram_size;
151}
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#if defined(CONFIG_SYS_DRAM_TEST)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500154int testdram (void)
155{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
157 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500158 uint *p;
159
160 printf("SDRAM test phase 1:\n");
161 for (p = pstart; p < pend; p++)
162 *p = 0xaaaaaaaa;
163
164 for (p = pstart; p < pend; p++) {
165 if (*p != 0xaaaaaaaa) {
166 printf ("SDRAM test fails at: %08x\n", (uint) p);
167 return 1;
168 }
169 }
170
171 printf("SDRAM test phase 2:\n");
172 for (p = pstart; p < pend; p++)
173 *p = 0x55555555;
174
175 for (p = pstart; p < pend; p++) {
176 if (*p != 0x55555555) {
177 printf ("SDRAM test fails at: %08x\n", (uint) p);
178 return 1;
179 }
180 }
181
182 printf("SDRAM test passed.\n");
183 return 0;
184}
185#endif
186
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500187#if !defined(CONFIG_SPD_EEPROM)
188/*************************************************************************
189 * fixed sdram init -- doesn't use serial presence detect.
190 ************************************************************************/
191long int fixed_sdram (void)
192{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#ifndef CONFIG_SYS_RAMBOOT
194 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
197 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
198 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
199 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
200 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
201 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500202#if defined (CONFIG_DDR_ECC)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500203 ddr->err_disable = 0x0000000D;
204 ddr->err_sbe = 0x00ff0000;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500205#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500206 asm("sync;isync;msync");
207 udelay(500);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500208#if defined (CONFIG_DDR_ECC)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500209 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500211#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500213#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500214 asm("sync; isync; msync");
215 udelay(500);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500216#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217 return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500218}
219#endif /* !defined(CONFIG_SPD_EEPROM) */
Ben Warren8ca0b3f2008-08-31 10:45:44 -0700220
221int board_eth_init(bd_t *bis)
222{
223 /*
224 * This board either has PCI NICs or uses the CPU's TSECs
225 * pci_eth_init() will return 0 if no NICs found, so in that case
226 * returning -1 will force cpu_eth_init() to be called.
227 */
228 int num = pci_eth_init(bis);
229 return (num <= 0 ? -1 : num);
230}