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Nishanth Menon3e48d372022-05-25 13:38:48 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM625 SK dts file for SPLs
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Neha Malcom Francisce46f512023-07-22 00:14:38 +05307#include "k3-am625-sk-binman.dtsi"
8
Nishanth Menon3e48d372022-05-25 13:38:48 +05309/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
Nishanth Menon7937af12023-07-27 04:03:31 -050012 tick-timer = &main_timer0;
Nishanth Menon3e48d372022-05-25 13:38:48 +053013 };
14
15 aliases {
16 mmc1 = &sdhci1;
17 };
Georgi Vlaev362b0d22022-06-14 17:45:31 +030018
19 memory@80000000 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030020 bootph-all;
Georgi Vlaev362b0d22022-06-14 17:45:31 +030021 };
Nishanth Menon3e48d372022-05-25 13:38:48 +053022};
23
Nishanth Menon7937af12023-07-27 04:03:31 -050024&cbass_main {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030025 bootph-all;
Nishanth Menon7937af12023-07-27 04:03:31 -050026};
Nishanth Menon3e48d372022-05-25 13:38:48 +053027
Nishanth Menon7937af12023-07-27 04:03:31 -050028&main_timer0 {
29 clock-frequency = <25000000>;
Roger Quadros7e5b6f12023-09-29 16:46:45 +030030 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053031};
32
33&dmss {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030034 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053035};
36
37&secure_proxy_main {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030038 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053039};
40
41&dmsc {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030042 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053043};
44
45&k3_pds {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030046 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053047};
48
49&k3_clks {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030050 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053051};
52
53&k3_reset {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030054 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053055};
56
57&wkup_conf {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030058 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053059};
60
61&chipid {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030062 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053063};
64
65&main_pmx0 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030066 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053067};
68
69&main_uart0 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030070 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053071};
72
73&main_uart0_pins_default {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030074 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053075};
76
Nishanth Menon3e48d372022-05-25 13:38:48 +053077&cbass_mcu {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030078 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053079};
80
81&cbass_wakeup {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030082 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053083};
84
85&mcu_pmx0 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030086 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053087};
88
Nishanth Menon3e48d372022-05-25 13:38:48 +053089&sdhci1 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030090 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053091};
92
93&main_mmc1_pins_default {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030094 bootph-all;
Nishanth Menon3e48d372022-05-25 13:38:48 +053095};
Dhruva Gole8994ac32022-10-27 20:23:10 +053096
97&fss {
Roger Quadros7e5b6f12023-09-29 16:46:45 +030098 bootph-all;
Dhruva Gole8994ac32022-10-27 20:23:10 +053099};
100
101&ospi0_pins_default {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300102 bootph-all;
Dhruva Gole8994ac32022-10-27 20:23:10 +0530103};
104
105&ospi0 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300106 bootph-all;
Dhruva Gole8994ac32022-10-27 20:23:10 +0530107
108 flash@0 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300109 bootph-all;
Dhruva Gole8994ac32022-10-27 20:23:10 +0530110
111 partitions {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300112 bootph-all;
Dhruva Gole8994ac32022-10-27 20:23:10 +0530113
114 partition@3fc0000 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300115 bootph-all;
Dhruva Gole8994ac32022-10-27 20:23:10 +0530116 };
117 };
118 };
119};
Sjoerd Simons39248d32022-12-20 16:21:45 +0100120
121&cpsw3g {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300122 bootph-all;
Sjoerd Simons39248d32022-12-20 16:21:45 +0100123};
124
125&cpsw_port1 {
Roger Quadros7e5b6f12023-09-29 16:46:45 +0300126 bootph-all;
Sjoerd Simons39248d32022-12-20 16:21:45 +0100127};
128
129&cpsw_port2 {
130 status = "disabled";
131};