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wdenka56bd922004-06-06 23:13:55 +00001/*
wdenk1eaeb582004-06-08 00:22:43 +00002 * (C) Copyright 2003-2004
wdenka56bd922004-06-06 23:13:55 +00003 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk1eaeb582004-06-08 00:22:43 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenka56bd922004-06-06 23:13:55 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
wdenka56bd922004-06-06 23:13:55 +000030/* allow to overwrite serial and ethaddr */
31#define CONFIG_ENV_OVERWRITE
32
wdenka56bd922004-06-06 23:13:55 +000033/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
wdenk1eaeb582004-06-08 00:22:43 +000038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP730 1 /* which is in a 730 */
41#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
wdenka56bd922004-06-06 23:13:55 +000042
wdenk1eaeb582004-06-08 00:22:43 +000043/*
44 * Input clock of PLL
45 * The OMAP730 Perseus 2 has 13MHz input clock
wdenka56bd922004-06-06 23:13:55 +000046 */
47
wdenk1eaeb582004-06-08 00:22:43 +000048#define CONFIG_SYS_CLK_FREQ 13000000
wdenka56bd922004-06-06 23:13:55 +000049
wdenk1eaeb582004-06-08 00:22:43 +000050#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenka56bd922004-06-06 23:13:55 +000051
wdenk1eaeb582004-06-08 00:22:43 +000052#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenka56bd922004-06-06 23:13:55 +000053#define CONFIG_SETUP_MEMORY_TAGS 1
54
wdenka56bd922004-06-06 23:13:55 +000055/*
56 * Size of malloc() pool
57 */
58
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenka56bd922004-06-06 23:13:55 +000060
61/*
62 * Hardware drivers
63 */
64
Nishanth Menonac6b3622009-10-16 00:06:37 -050065#define CONFIG_LAN91C96
wdenk1eaeb582004-06-08 00:22:43 +000066#define CONFIG_LAN91C96_BASE 0x04000300
wdenka56bd922004-06-06 23:13:55 +000067#define CONFIG_LAN91C96_EXT_PHY
68
wdenka56bd922004-06-06 23:13:55 +000069/*
70 * NS16550 Configuration
71 */
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_NS16550
74#define CONFIG_SYS_NS16550_SERIAL
75#define CONFIG_SYS_NS16550_REG_SIZE (1)
76#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
77#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk1eaeb582004-06-08 00:22:43 +000078 * on perseus */
wdenka56bd922004-06-06 23:13:55 +000079
80/*
81 * select serial console configuration
82 */
83
wdenk1eaeb582004-06-08 00:22:43 +000084#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
wdenka56bd922004-06-06 23:13:55 +000085
wdenk1eaeb582004-06-08 00:22:43 +000086#define CONFIG_CONS_INDEX 1
87#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenka56bd922004-06-06 23:13:55 +000089
wdenka56bd922004-06-06 23:13:55 +000090
wdenk1eaeb582004-06-08 00:22:43 +000091/*
Jon Loeligera5cb2302007-07-04 22:33:13 -050092 * Command line configuration.
wdenka56bd922004-06-06 23:13:55 +000093 */
Jon Loeligera5cb2302007-07-04 22:33:13 -050094#include <config_cmd_default.h>
wdenka56bd922004-06-06 23:13:55 +000095
Jon Loeligera5cb2302007-07-04 22:33:13 -050096#define CONFIG_CMD_DHCP
97
98
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050099/*
100 * BOOTP options
101 */
102#define CONFIG_BOOTP_SUBNETMASK
103#define CONFIG_BOOTP_GATEWAY
104#define CONFIG_BOOTP_HOSTNAME
105#define CONFIG_BOOTP_BOOTPATH
106
Jon Loeligera5cb2302007-07-04 22:33:13 -0500107
wdenka56bd922004-06-06 23:13:55 +0000108#include <configs/omap730.h>
109#include <configs/h2_p2_dbg_board.h>
110
wdenk1eaeb582004-06-08 00:22:43 +0000111#define CONFIG_BOOTDELAY 3
112#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
wdenka56bd922004-06-06 23:13:55 +0000113
wdenk1eaeb582004-06-08 00:22:43 +0000114#define CONFIG_LOADADDR 0x10000000
wdenka56bd922004-06-06 23:13:55 +0000115
116#define CONFIG_ETHADDR
wdenk1eaeb582004-06-08 00:22:43 +0000117#define CONFIG_NETMASK 255.255.255.0
118#define CONFIG_IPADDR 192.168.0.23
119#define CONFIG_SERVERIP 192.150.0.100
120#define CONFIG_BOOTFILE "uImage" /* File to load */
wdenka56bd922004-06-06 23:13:55 +0000121
Jon Loeligera5cb2302007-07-04 22:33:13 -0500122#if defined(CONFIG_CMD_KGDB)
wdenk1eaeb582004-06-08 00:22:43 +0000123#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
124#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
wdenka56bd922004-06-06 23:13:55 +0000125#endif
126
wdenka56bd922004-06-06 23:13:55 +0000127/*
128 * Miscellaneous configurable options
129 */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LONGHELP /* undef to save memory */
132#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
133#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000134/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
136#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
137#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenka56bd922004-06-06 23:13:55 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenka56bd922004-06-06 23:13:55 +0000143
wdenk1eaeb582004-06-08 00:22:43 +0000144/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
145 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
wdenka56bd922004-06-06 23:13:55 +0000146 * local divisor.
147 */
Ladislav Michl81472d82009-03-30 18:58:41 +0200148#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
149#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
150#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
wdenka56bd922004-06-06 23:13:55 +0000151
152/*-----------------------------------------------------------------------
153 * Stack sizes
154 *
155 * The stack sizes are set up in start.S using the settings below
156 */
157
wdenk1eaeb582004-06-08 00:22:43 +0000158#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenka56bd922004-06-06 23:13:55 +0000159#ifdef CONFIG_USE_IRQ
wdenk1eaeb582004-06-08 00:22:43 +0000160#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
161#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenka56bd922004-06-06 23:13:55 +0000162#endif
163
wdenka56bd922004-06-06 23:13:55 +0000164/*-----------------------------------------------------------------------
165 * Physical Memory Map
166 */
167
wdenk1eaeb582004-06-08 00:22:43 +0000168#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
169#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
170#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
wdenka56bd922004-06-06 23:13:55 +0000171
172#if defined(CONFIG_CS0_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000173#define PHYS_FLASH_1 0x0C000000
wdenka56bd922004-06-06 23:13:55 +0000174#elif defined(CONFIG_CS3_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000175#define PHYS_FLASH_1 0x00000000
wdenka56bd922004-06-06 23:13:55 +0000176#else
177#error Unknown Boot Chip-Select number
178#endif
179
Aneesh V154f5342011-06-09 08:54:57 -0400180#define PHYS_SRAM 0x20000000
181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenka56bd922004-06-06 23:13:55 +0000183
184/*-----------------------------------------------------------------------
185 * FLASH and environment organization
186 */
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk1eaeb582004-06-08 00:22:43 +0000189#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
wdenka56bd922004-06-06 23:13:55 +0000191/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
wdenka56bd922004-06-06 23:13:55 +0000193
194/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
196#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenka56bd922004-06-06 23:13:55 +0000197
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200198#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200199#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
200#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenka56bd922004-06-06 23:13:55 +0000201
Aneesh V154f5342011-06-09 08:54:57 -0400202#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
203#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
204
wdenk1eaeb582004-06-08 00:22:43 +0000205#endif /* ! __CONFIG_H */