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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7ebf7443ad018a0647f549a835a55f0c08d7a15d / . / board / pm826 / pm826.c
blob: c59b0284094fe0fdfab835473cb22297f3b27806 [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
28/*
29 * I/O Port configuration table
30 *
31 * if conf is 1, then that port pin will be configured at boot time
32 * according to the five values podr/pdir/ppar/psor/pdat for that entry
33 */
34
35const iop_conf_t iop_conf_tab[4][32] = {
36
37 /* Port A configuration */
38 { /* conf ppar psor pdir podr pdat */
39 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
40 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
41 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
42 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
43 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
44 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
45 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
46 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
47 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
48 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
49 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
50 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
51 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
52 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
53 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
54 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
55 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
56 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
57 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
58 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
59 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
60 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
61 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
62 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
63 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
64 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
65 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
66 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
67 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
68 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
69 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
70 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
71 },
72
73 /* Port B configuration */
74 { /* conf ppar psor pdir podr pdat */
75 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* PB31 */
76 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* PB30 */
77 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* PB29 */
78 /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
79 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* PB27 */
80 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* PB26 */
81 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* PB25 */
82 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* PB24 */
83 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* PB23 */
84 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* PB22 */
85 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* PB21 */
86 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* PB20 */
87 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* PB19 */
88 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* PB18 */
89 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
90 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
91 /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
92 /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
93 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
94 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
95 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
96 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
97 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
98 /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
99 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
100 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
101 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
102 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
103 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
104 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
105 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
106 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
107 },
108
109 /* Port C */
110 { /* conf ppar psor pdir podr pdat */
111 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
112 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
113 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
114 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
115 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
116 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
117 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
118 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
119 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
120 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
121 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
122 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* PC20 */
123 /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* PC19 */
124 /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* PC18 */
125 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
126 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
127 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
128 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
129 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
130 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
131 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
132 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
133 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
134 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
135 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
136 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
137 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
138 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
139 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
140 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
141 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
142 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
143 },
144
145 /* Port D */
146 { /* conf ppar psor pdir podr pdat */
147 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
148 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
149 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
150 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
151 /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
152 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
153 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
154 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
155 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
156 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
157 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
158 /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
159 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
160 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
161 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
162 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
163#if defined(CONFIG_SOFT_I2C)
164 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
165 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
166#else
167#if defined(CONFIG_HARD_I2C)
168 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
169 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
170#else /* normal I/O port pins */
171 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
172 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
173#endif
174#endif
175 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
176 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
177 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
178 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
179 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
180 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
181 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
182 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
183 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
184 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
185 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
186 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
187 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
188 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
189 }
190};
191
192/* ------------------------------------------------------------------------- */
193
194/* Check Board Identity:
195 */
196int checkboard (void)
197{
198 puts ("Board: PM826\n");
199 return 0;
200}
201
202/* ------------------------------------------------------------------------- */
203
204
205/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
206 *
207 * This routine performs standard 8260 initialization sequence
208 * and calculates the available memory size. It may be called
209 * several times to try different SDRAM configurations on both
210 * 60x and local buses.
211 */
212static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
213 ulong orx, volatile uchar * base)
214{
215 volatile uchar c = 0xff;
216 volatile ulong cnt, val;
217 volatile ulong *addr;
218 volatile uint *sdmr_ptr;
219 volatile uint *orx_ptr;
220 int i;
221 ulong save[32]; /* to make test non-destructive */
222 ulong maxsize;
223
224 /* We must be able to test a location outsize the maximum legal size
225 * to find out THAT we are outside; but this address still has to be
226 * mapped by the controller. That means, that the initial mapping has
227 * to be (at least) twice as large as the maximum expected size.
228 */
229 maxsize = (1 + (~orx | 0x7fff)) / 2;
230
231 sdmr_ptr = &memctl->memc_psdmr;
232 orx_ptr = &memctl->memc_or2;
233
234 *orx_ptr = orx;
235
236 /*
237 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
238 *
239 * "At system reset, initialization software must set up the
240 * programmable parameters in the memory controller banks registers
241 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
242 * system software should execute the following initialization sequence
243 * for each SDRAM device.
244 *
245 * 1. Issue a PRECHARGE-ALL-BANKS command
246 * 2. Issue eight CBR REFRESH commands
247 * 3. Issue a MODE-SET command to initialize the mode register
248 *
249 * The initial commands are executed by setting P/LSDMR[OP] and
250 * accessing the SDRAM with a single-byte transaction."
251 *
252 * The appropriate BRx/ORx registers have already been set when we
253 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
254 */
255
256 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
257 *base = c;
258
259 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
260 for (i = 0; i < 8; i++)
261 *base = c;
262
263 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
264 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
265
266 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
267 *base = c;
268
269 /*
270 * Check memory range for valid RAM. A simple memory test determines
271 * the actually available RAM size between addresses `base' and
272 * `base + maxsize'. Some (not all) hardware errors are detected:
273 * - short between address lines
274 * - short between data lines
275 */
276 i = 0;
277 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
278 addr = (volatile ulong *) base + cnt; /* pointer arith! */
279 save[i++] = *addr;
280 *addr = ~cnt;
281 }
282
283 addr = (volatile ulong *) base;
284 save[i] = *addr;
285 *addr = 0;
286
287 if ((val = *addr) != 0) {
288 *addr = save[i];
289 return (0);
290 }
291
292 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
293 addr = (volatile ulong *) base + cnt; /* pointer arith! */
294 val = *addr;
295 *addr = save[--i];
296 if (val != ~cnt) {
297 /* Write the actual size to ORx
298 */
299 *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
300 return (cnt * sizeof (long));
301 }
302 }
303 return (maxsize);
304}
305
306
307long int initdram (int board_type)
308{
309 volatile immap_t *immap = (immap_t *) CFG_IMMR;
310 volatile memctl8260_t *memctl = &immap->im_memctl;
311
312#ifndef CFG_RAMBOOT
313 ulong size8, size9;
314#endif
315 ulong psize = 32 * 1024 * 1024;
316
317 memctl->memc_psrt = CFG_PSRT;
318 memctl->memc_mptpr = CFG_MPTPR;
319
320#ifndef CFG_RAMBOOT
321 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
322 (uchar *) CFG_SDRAM_BASE);
323 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
324 (uchar *) CFG_SDRAM_BASE);
325
326 if (size8 < size9) {
327 psize = size9;
328 printf ("(60x:9COL) ");
329 } else {
330 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
331 (uchar *) CFG_SDRAM_BASE);
332 printf ("(60x:8COL) ");
333 }
334#endif
335 return (psize);
336}
337
338#if (CONFIG_COMMANDS & CFG_CMD_DOC)
339extern void doc_probe (ulong physadr);
340void doc_init (void)
341{
342 doc_probe (CFG_DOC_BASE);
343}
344#endif