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wdenk0db5bca2003-03-31 17:27:09 +00001/*
2 * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
wdenk8bde7f72003-06-27 21:31:46 +000019 * Foundation,
wdenk0db5bca2003-03-31 17:27:09 +000020 */
21
22/*
23 * File: cpu_init.c
wdenk8bde7f72003-06-27 21:31:46 +000024 *
wdenk0db5bca2003-03-31 17:27:09 +000025 * Discription: Contains initialisation functions to setup
Wolfgang Denk53677ef2008-05-20 16:00:29 +020026 * the cpu properly
wdenk0db5bca2003-03-31 17:27:09 +000027 *
28 */
29
30#include <common.h>
31#include <mpc5xx.h>
32#include <watchdog.h>
33
34/*
wdenk8bde7f72003-06-27 21:31:46 +000035 * Setup essential cpu registers to run
wdenk0db5bca2003-03-31 17:27:09 +000036 */
37void cpu_init_f (volatile immap_t * immr)
38{
39 volatile memctl5xx_t *memctl = &immr->im_memctl;
40 ulong reg;
41
42 /* SYPCR - contains watchdog control. This will enable watchdog */
43 /* if CONFIG_WATCHDOG is set */
44 immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
45
46#if defined(CONFIG_WATCHDOG)
47 reset_5xx_watchdog (immr);
wdenk8bde7f72003-06-27 21:31:46 +000048#endif
wdenk0db5bca2003-03-31 17:27:09 +000049
50 /* SIUMCR - contains debug pin configuration */
51 immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
52
53 /* Initialize timebase. Unlock TBSCRK */
54 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
55 immr->im_sit.sit_tbscr = CFG_TBSCR;
56
57 /* Full IMB bus speed */
58 immr->im_uimb.uimb_umcr = CFG_UMCR;
wdenk8bde7f72003-06-27 21:31:46 +000059
wdenk0db5bca2003-03-31 17:27:09 +000060 /* Time base and decrementer will be enables (TBE) */
61 /* in init_timebase() in time.c called from board_init_f(). */
wdenk8bde7f72003-06-27 21:31:46 +000062
wdenk0db5bca2003-03-31 17:27:09 +000063 /* Initialize the PIT. Unlock PISCRK */
64 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
65 immr->im_sit.sit_piscr = CFG_PISCR;
66
wdenkb6e4c402004-01-02 16:05:07 +000067#if !defined(CONFIG_PATI)
68 /* PATI sest PLL in start.S */
wdenk0db5bca2003-03-31 17:27:09 +000069 /* PLL (CPU clock) settings */
70 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
71
72 /* If CFG_PLPRCR (set in the various *_config.h files) tries to
73 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
74 * otherwise OR in CFG_PLPRCR so we do not change the currentMF
75 * field value.
76 */
77#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
78 reg = CFG_PLPRCR; /* reset control bits */
79#else
80 reg = immr->im_clkrst.car_plprcr;
81 reg &= PLPRCR_MF_MSK; /* isolate MF field */
82 reg |= CFG_PLPRCR; /* reset control bits */
83#endif
84 immr->im_clkrst.car_plprcr = reg;
85
wdenkb6e4c402004-01-02 16:05:07 +000086#endif /* !defined(CONFIG_PATI) */
87
wdenk0db5bca2003-03-31 17:27:09 +000088 /* System integration timers. CFG_MASK has EBDF configuration */
89 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
90 reg = immr->im_clkrst.car_sccr;
91 reg &= SCCR_MASK;
92 reg |= CFG_SCCR;
93 immr->im_clkrst.car_sccr = reg;
94
95 /* Memory Controller */
96 memctl->memc_br0 = CFG_BR0_PRELIM;
97 memctl->memc_or0 = CFG_OR0_PRELIM;
98
99#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
100 memctl->memc_or1 = CFG_OR1_PRELIM;
101 memctl->memc_br1 = CFG_BR1_PRELIM;
102#endif
103
104#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
105 memctl->memc_or2 = CFG_OR2_PRELIM;
106 memctl->memc_br2 = CFG_BR2_PRELIM;
107#endif
108
109#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
110 memctl->memc_or3 = CFG_OR3_PRELIM;
111 memctl->memc_br3 = CFG_BR3_PRELIM;
112#endif
113
114}
115
116/*
117 * Initialize higher level parts of cpu
118 */
119int cpu_init_r (void)
120{
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200121 /* Nothing to do at the moment */
wdenk0db5bca2003-03-31 17:27:09 +0000122 return (0);
123}