blob: d8b10f035808b29ef8500a365dae0786e7175568 [file] [log] [blame]
Weijie Gaoed86e4f2022-09-09 19:59:11 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <init.h>
8#include <asm/armv8/mmu.h>
9#include <asm/system.h>
10#include <asm/global_data.h>
Tom Rini15713fc2022-10-28 20:27:08 -040011#include <linux/sizes.h>
Weijie Gaoed86e4f2022-09-09 19:59:11 +080012
13DECLARE_GLOBAL_DATA_PTR;
14
15int dram_init(void)
16{
Tom Riniaa6e94d2022-11-16 13:10:37 -050017 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
Weijie Gaoed86e4f2022-09-09 19:59:11 +080018
19 return 0;
20}
21
22void reset_cpu(ulong addr)
23{
24 psci_system_reset();
25}
26
27static struct mm_region mt7981_mem_map[] = {
28 {
29 /* DDR */
30 .virt = 0x40000000UL,
31 .phys = 0x40000000UL,
32 .size = 0x80000000UL,
33 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
34 }, {
35 .virt = 0x00000000UL,
36 .phys = 0x00000000UL,
37 .size = 0x40000000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 PTE_BLOCK_NON_SHARE |
40 PTE_BLOCK_PXN | PTE_BLOCK_UXN
41 }, {
42 0,
43 }
44};
45
46struct mm_region *mem_map = mt7981_mem_map;