Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Bluewater Systems Snapper 9260 and 9G20 modules |
| 4 | * |
| 5 | * (C) Copyright 2011 Bluewater Systems |
| 6 | * Author: Andre Renaud <andre@bluewatersys.com> |
| 7 | * Author: Ryan Mallon <ryan@bluewatersys.com> |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | /* SoC type is defined in boards.cfg */ |
| 14 | #include <asm/hardware.h> |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 15 | #include <linux/sizes.h> |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 16 | |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 17 | /* ARM asynchronous clock */ |
| 18 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ |
| 19 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 20 | |
| 21 | /* CPU */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 22 | |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 23 | /* SDRAM */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 24 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 25 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ |
| 26 | #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ |
| 27 | GENERATED_GBL_DATA_SIZE) |
| 28 | |
| 29 | /* Mem test settings */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 30 | |
| 31 | /* NAND Flash */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 32 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 33 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 34 | #define CONFIG_SYS_NAND_DBW_8 |
| 35 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ |
| 36 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ |
| 37 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 |
| 38 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 |
| 39 | |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 40 | /* USB */ |
| 41 | #define CONFIG_USB_ATMEL |
Bo Shen | dcd2f1a | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 42 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 43 | #define CONFIG_USB_OHCI_NEW |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 44 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 45 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE |
| 46 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" |
| 47 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 48 | |
| 49 | /* GPIOs and IO expander */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 50 | #define CONFIG_PCA953X |
| 51 | #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 |
| 52 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } |
| 53 | |
| 54 | /* UARTs/Serial console */ |
Simon Glass | 1a1927f | 2014-10-29 13:09:01 -0600 | [diff] [blame] | 55 | #ifndef CONFIG_DM_SERIAL |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 56 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 57 | #define CONFIG_USART_ID ATMEL_ID_SYS |
Simon Glass | 1a1927f | 2014-10-29 13:09:01 -0600 | [diff] [blame] | 58 | #endif |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 59 | |
| 60 | /* I2C - Bit-bashed */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 61 | #define CONFIG_SOFT_I2C_READ_REPEATED_START |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 62 | #define I2C_INIT do { \ |
| 63 | at91_set_gpio_output(AT91_PIN_PA23, 1); \ |
| 64 | at91_set_gpio_output(AT91_PIN_PA24, 1); \ |
| 65 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ |
| 66 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ |
| 67 | } while (0) |
| 68 | #define I2C_SOFT_DECLARATIONS |
| 69 | #define I2C_ACTIVE |
| 70 | #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); |
| 71 | #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); |
| 72 | #define I2C_SDA(bit) do { \ |
| 73 | if (bit) { \ |
| 74 | at91_set_gpio_input(AT91_PIN_PA23, 1); \ |
| 75 | } else { \ |
| 76 | at91_set_gpio_output(AT91_PIN_PA23, 1); \ |
| 77 | at91_set_gpio_value(AT91_PIN_PA23, bit); \ |
| 78 | } \ |
| 79 | } while (0) |
| 80 | #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) |
| 81 | #define I2C_DELAY udelay(2) |
| 82 | |
| 83 | /* Boot options */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 84 | |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 85 | /* Environment settings */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 86 | |
| 87 | /* Console settings */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 88 | |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 89 | #endif /* __CONFIG_H */ |