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wdenk0e6d7982004-03-14 00:07:33 +00001/*
2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
3 *
Stefan Roese8a316c92005-08-01 16:49:12 +02004 * (C) Copyright 2005
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 *
wdenk0e6d7982004-03-14 00:07:33 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
wdenk42dfe7a2004-03-14 22:25:36 +000027 * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
wdenk0e6d7982004-03-14 00:07:33 +000028 * Adapted to current Das U-Boot source
29 ***********************************************************************/
30
31
32/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020033 * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
wdenk0e6d7982004-03-14 00:07:33 +000034 ***********************************************************************/
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*-----------------------------------------------------------------------
40 * High Level Configuration Options
41 *----------------------------------------------------------------------*/
42#define CONFIG_OCOTEA 1 /* Board is ebony */
Stefan Roese846b0dd2005-08-08 12:42:22 +020043#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020044#define CONFIG_440 1 /* ... PPC440 family */
wdenk0e6d7982004-03-14 00:07:33 +000045#define CONFIG_4xx 1 /* ... PPC4xx family */
46#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
47#undef CFG_DRAM_TEST /* Disable-takes long time! */
48#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
49
50/*-----------------------------------------------------------------------
51 * Base addresses -- Note these are effective addresses where the
52 * actual resources get mapped (not physical addresses)
53 *----------------------------------------------------------------------*/
54#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
55#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
stroese7ec25502005-04-07 05:35:12 +000056#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
wdenk0e6d7982004-03-14 00:07:33 +000057#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
58#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
59#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
60#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
61
62#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
63#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
64
65/*-----------------------------------------------------------------------
66 * Initial RAM & stack pointer (placed in internal SRAM)
67 *----------------------------------------------------------------------*/
68#define CFG_TEMP_STACK_OCM 1
69#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
70#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
71#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
72#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
73
74#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk42dfe7a2004-03-14 22:25:36 +000075#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
76#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
wdenk0e6d7982004-03-14 00:07:33 +000077
78#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
79#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
80
81/*-----------------------------------------------------------------------
82 * Serial Port
83 *----------------------------------------------------------------------*/
84#undef CONFIG_SERIAL_SOFTWARE_FIFO
85#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
86#define CONFIG_BAUDRATE 115200
87
88#define CFG_BAUDRATE_TABLE \
89 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
90
91/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +020092 * Environment
93 *----------------------------------------------------------------------*/
94/*
95 * Define here the location of the environment variables (FLASH or NVRAM).
96 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
97 * supported for backward compatibility.
98 */
99#if 1
100#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
101#else
102#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
103#endif
104
105
106/*-----------------------------------------------------------------------
wdenk0e6d7982004-03-14 00:07:33 +0000107 * NVRAM/RTC
108 *
109 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
110 * The DS1743 code assumes this condition (i.e. -- it assumes the base
111 * address for the RTC registers is:
112 *
113 * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
114 *
115 *----------------------------------------------------------------------*/
116#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
117#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
118
Stefan Roese8a316c92005-08-01 16:49:12 +0200119#ifdef CFG_ENV_IS_IN_NVRAM
120#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
121#define CFG_ENV_ADDR \
122 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
123#endif /* CFG_ENV_IS_IN_NVRAM */
124
wdenk0e6d7982004-03-14 00:07:33 +0000125/*-----------------------------------------------------------------------
126 * FLASH related
127 *----------------------------------------------------------------------*/
128#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
129#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
130
131#undef CFG_FLASH_CHECKSUM
132#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
133#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
134
Stefan Roese8a316c92005-08-01 16:49:12 +0200135#define CFG_FLASH_ADDR0 0x5555
136#define CFG_FLASH_ADDR1 0x2aaa
137#define CFG_FLASH_WORD_SIZE unsigned char
138
139#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200140#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200141#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
142#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
143
144/* Address and size of Redundant Environment Sector */
145#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
146#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
147#endif /* CFG_ENV_IS_IN_FLASH */
148
wdenk0e6d7982004-03-14 00:07:33 +0000149/*-----------------------------------------------------------------------
150 * DDR SDRAM
151 *----------------------------------------------------------------------*/
Stefan Roesefa1aef12007-03-07 16:43:00 +0100152#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
wdenk42dfe7a2004-03-14 22:25:36 +0000153#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
Stefan Roesefa1aef12007-03-07 16:43:00 +0100154#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
wdenk0e6d7982004-03-14 00:07:33 +0000155
156/*-----------------------------------------------------------------------
157 * I2C
158 *----------------------------------------------------------------------*/
159#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
160#undef CONFIG_SOFT_I2C /* I2C bit-banged */
161#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
162#define CFG_I2C_SLAVE 0x7F
Stefan Roese4f92ed52006-08-07 14:33:32 +0200163
164#define CFG_I2C_MULTI_EEPROMS
165#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
166#define CFG_I2C_EEPROM_ADDR_LEN 1
167#define CFG_EEPROM_PAGE_WRITE_ENABLE
168#define CFG_EEPROM_PAGE_WRITE_BITS 3
169#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk0e6d7982004-03-14 00:07:33 +0000170
Stefan Roese8a316c92005-08-01 16:49:12 +0200171#define CONFIG_PREBOOT "echo;" \
172 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
173 "echo"
wdenk0e6d7982004-03-14 00:07:33 +0000174
Stefan Roese8a316c92005-08-01 16:49:12 +0200175#undef CONFIG_BOOTARGS
wdenk0e6d7982004-03-14 00:07:33 +0000176
Stefan Roese8a316c92005-08-01 16:49:12 +0200177#define CONFIG_EXTRA_ENV_SETTINGS \
178 "netdev=eth0\0" \
179 "hostname=ocotea\0" \
180 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100181 "nfsroot=${serverip}:${rootpath}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200182 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100183 "addip=setenv bootargs ${bootargs} " \
184 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
185 ":${hostname}:${netdev}:off panic=1\0" \
186 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese8a316c92005-08-01 16:49:12 +0200187 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100188 "bootm ${kernel_addr}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200189 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100190 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
191 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200192 "bootm\0" \
193 "rootpath=/opt/eldk/ppc_4xx\0" \
194 "bootfile=/tftpboot/ocotea/uImage\0" \
195 "kernel_addr=fff00000\0" \
196 "ramdisk_addr=fff10000\0" \
Stefan Roese5a753f92007-02-07 16:51:08 +0100197 "initrd_high=30000000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200198 "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
199 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
200 "cp.b 100000 fffc0000 40000;" \
201 "setenv filesize;saveenv\0" \
202 "upd=run load;run update\0" \
203 ""
204#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk0e6d7982004-03-14 00:07:33 +0000205
Stefan Roese8a316c92005-08-01 16:49:12 +0200206#if 0
207#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
208#else
209#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
210#endif
211
wdenk0e6d7982004-03-14 00:07:33 +0000212#define CONFIG_BAUDRATE 115200
213
214#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
215#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
216
217#define CONFIG_MII 1 /* MII PHY management */
218#define CONFIG_NET_MULTI 1
219#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
wdenk42dfe7a2004-03-14 22:25:36 +0000220#define CONFIG_PHY1_ADDR 2
221#define CONFIG_PHY2_ADDR 0x10
222#define CONFIG_PHY3_ADDR 0x18
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200223#define CONFIG_HAS_ETH0
224#define CONFIG_HAS_ETH1
225#define CONFIG_HAS_ETH2
226#define CONFIG_HAS_ETH3
wdenk42dfe7a2004-03-14 22:25:36 +0000227#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
wdenk6fb6af62004-03-23 23:20:24 +0000228#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200229#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
230#define CONFIG_PHY_RESET_DELAY 1000
Stefan Roese4f92ed52006-08-07 14:33:32 +0200231#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
232
233#define CONFIG_NETCONSOLE /* include NetConsole support */
wdenk0e6d7982004-03-14 00:07:33 +0000234
wdenk0e6d7982004-03-14 00:07:33 +0000235
Jon Loeligera5cb2302007-07-04 22:33:13 -0500236/*
237 * Command line configuration.
238 */
239#include <config_cmd_default.h>
240
241#define CONFIG_CMD_ASKENV
242#define CONFIG_CMD_DATE
243#define CONFIG_CMD_DHCP
244#define CONFIG_CMD_DIAG
245#define CONFIG_CMD_ELF
246#define CONFIG_CMD_EEPROM
247#define CONFIG_CMD_I2C
248#define CONFIG_CMD_IRQ
249#define CONFIG_CMD_MII
250#define CONFIG_CMD_NET
251#define CONFIG_CMD_NFS
252#define CONFIG_CMD_PCI
253#define CONFIG_CMD_PING
254#define CONFIG_CMD_REGINFO
255#define CONFIG_CMD_SDRAM
256#define CONFIG_CMD_SNTP
257
wdenk0e6d7982004-03-14 00:07:33 +0000258
259#undef CONFIG_WATCHDOG /* watchdog disabled */
260
261/*
262 * Miscellaneous configurable options
263 */
264#define CFG_LONGHELP /* undef to save memory */
265#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5cb2302007-07-04 22:33:13 -0500266#if defined(CONFIG_CMD_KGDB)
wdenk0e6d7982004-03-14 00:07:33 +0000267#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
268#else
269#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
270#endif
271#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
272#define CFG_MAXARGS 16 /* max number of command args */
273#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
274
275#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
276#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
277
278#define CFG_LOAD_ADDR 0x100000 /* default load address */
279#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
280
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200281#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0e6d7982004-03-14 00:07:33 +0000282
Stefan Roese4f92ed52006-08-07 14:33:32 +0200283#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese8a316c92005-08-01 16:49:12 +0200284#define CONFIG_LOOPW 1 /* enable loopw command */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200285#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese8a316c92005-08-01 16:49:12 +0200286#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
287#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
288
wdenk0e6d7982004-03-14 00:07:33 +0000289/*-----------------------------------------------------------------------
290 * PCI stuff
291 *-----------------------------------------------------------------------
292 */
293/* General PCI */
Stefan Roese8a316c92005-08-01 16:49:12 +0200294#define CONFIG_PCI /* include pci support */
295#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk42dfe7a2004-03-14 22:25:36 +0000296#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
297#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
wdenk0e6d7982004-03-14 00:07:33 +0000298
299/* Board-specific PCI */
Stefan Roese8a316c92005-08-01 16:49:12 +0200300#define CFG_PCI_TARGET_INIT /* let board init pci target */
wdenk0e6d7982004-03-14 00:07:33 +0000301
Stefan Roese8a316c92005-08-01 16:49:12 +0200302#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
wdenk42dfe7a2004-03-14 22:25:36 +0000303#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
wdenk0e6d7982004-03-14 00:07:33 +0000304
305/*
306 * For booting Linux, the board info and command line data
307 * have to be in the first 8 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
309 */
310#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
311/*-----------------------------------------------------------------------
312 * Cache Configuration
313 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200314#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
wdenk0e6d7982004-03-14 00:07:33 +0000315#define CFG_CACHELINE_SIZE 32 /* ... */
Jon Loeligera5cb2302007-07-04 22:33:13 -0500316#if defined(CONFIG_CMD_KGDB)
wdenk0e6d7982004-03-14 00:07:33 +0000317#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
318#endif
319
320/*
321 * Internal Definitions
322 *
323 * Boot Flags
324 */
325#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
326#define BOOTFLAG_WARM 0x02 /* Software reboot */
327
Jon Loeligera5cb2302007-07-04 22:33:13 -0500328#if defined(CONFIG_CMD_KGDB)
wdenk0e6d7982004-03-14 00:07:33 +0000329#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
330#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
331#endif
332#endif /* __CONFIG_H */