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wdenk42d1f032003-10-15 23:53:47 +00001Motorola MPC8540ADS and MPC8560ADS board
2
wdenk9aea9532004-08-01 23:02:45 +00003Created 10/15/03 Xianghua Xiao
4Updated 13-July-2004 Jon Loeliger
wdenk42d1f032003-10-15 23:53:47 +00005-----------------------------------------
6
wdenk4654af22003-10-22 09:00:28 +000070. Toolchain
wdenk9aea9532004-08-01 23:02:45 +00008
9 The Binutils in current ELDK toolchain will not support MPC85xx
wdenk03f5c552004-10-10 21:21:55 +000010 chip. You need to use binutils-2.14.tar.bz2 (or newer) from
wdenk9aea9532004-08-01 23:02:45 +000011 http://ftp.gnu.org/gnu/binutils.
12
13 The 8540/8560 ADS code base is known to compile using:
14 gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
15
wdenk4654af22003-10-22 09:00:28 +000016
wdenk42d1f032003-10-15 23:53:47 +0000171. SWITCH SETTINGS & JUMPERS
wdenk48abe7b2004-06-09 10:15:00 +000018
wdenk9aea9532004-08-01 23:02:45 +0000191.0 Nomenclature
20
21 For some reason, the HW designers describe the switch settings
22 in terms of 0 and 1, and then map that to physical switches where
23 the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
24 Luckily, we're SW types and virtual settings are handled daily.
25
26 The switches for the Rev A board are numbered differently than
27 for the Pilot board. Oh yeah.
28
29 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
30 bits may contribute to signals that are numbered based at 0,
31 and some of those signals may be high-bit-number-0 too. Heed
32 well the names and labels and do not get confused.
33
34 "Off" == 1
35 "On" == 0
36
37 SW18 is switch 18 as silk-screened onto the board.
Thomas Weberc46bf092012-03-24 22:44:01 +000038 SW4[8] is the bit labeled 8 on Switch 4.
wdenk9aea9532004-08-01 23:02:45 +000039 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
40 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
41
421.1 For the MPC85xxADS Pilot Board
43
44 First, make sure the board default setting is consistent with the document
wdenk42d1f032003-10-15 23:53:47 +000045 shipped with your board. Then apply the following changes:
wdenk9aea9532004-08-01 23:02:45 +000046 SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
wdenk42d1f032003-10-15 23:53:47 +000047 SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
wdenk0ac6f8b2004-07-09 23:27:13 +000048 SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
wdenk547b4cb2004-06-09 00:51:50 +000049 SW11[7]='ON' (rev2), 'OFF' (rev1)
wdenk42d1f032003-10-15 23:53:47 +000050 SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
51 SW22[1-4]="OFF OFF ON OFF"
52 SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
53 J1 = "Enable Prog" (Make sure your flash is programmable for development)
wdenk48abe7b2004-06-09 10:15:00 +000054
wdenk9aea9532004-08-01 23:02:45 +000055 If you want to test PCI functionality with a 33Mhz PCI card, you will
wdenk547b4cb2004-06-09 00:51:50 +000056 have to change the system clock from the default 66Mhz to 33Mhz by
57 setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
58 double your platform clock(SW6) because the system clock is now only
wdenk0ac6f8b2004-07-09 23:27:13 +000059 half of its original value. For example, if at 66MHz your system
60 clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
wdenk48abe7b2004-06-09 10:15:00 +000061
wdenk9aea9532004-08-01 23:02:45 +000062 SW17[8] ------+ SW6
63 SW15[1] ----+ | [0:1]
64 V V V V
65 33MHz 1 1 1 0
66 66MHz 0 0 0 1
67
68 Hmmm... That SW6 setting description is incomplete but it works.
69
70
711.3 For the MPC85xxADS Rev A Board
72
73 As shipped, the board should be a 33MHz PCI bus with a CPU Clock
74 rate of 825 +/- fuzz:
75
76 Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
77
78 For 33MHz PCI, the switch settings should be like this:
79
80 SW18[7:1] = 0100001 = M==33 => 33MHz
81 SW18[8] = 1 => PWD Divider == 16
82 SW16[1:2] = 11 => N == 16 as PWD==1
83
84 Use the magical formula:
85 Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz
86
87 SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk
88 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
89
90
91 For 66MHz PCI, the switch settings should be like this:
92
93 SW18[7:1] = 0100001 = M==33 => 33MHz
94 SW18[8] = 0 => PWD Divider == 1
95 SW16[1:2] = 01 => N == 8 as PWD == 0
96
97 Use the magical formula:
98 Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz
99
100 SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
101 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
wdenk547b4cb2004-06-09 00:51:50 +0000102
Matthew McClintock38433cc2006-06-28 10:47:03 -0500103 In order to use PCI-X (only in the first PCI slot. The one with
104 the RIO connector), you need to set SW1[4] (config) to 1 (off).
105 Also, configure the board to run PCI at 66 MHz.
wdenk42d1f032003-10-15 23:53:47 +0000106
1072. MEMORY MAP TO WORK WITH LINUX KERNEL
wdenk547b4cb2004-06-09 00:51:50 +0000108
1092.1. For the initial bringup, we adopted a consistent memory scheme
Bin Menga1875592016-02-05 19:30:11 -0800110 between U-Boot and linux kernel, you can customize it based on your
wdenk547b4cb2004-06-09 00:51:50 +0000111 system requirements:
112
wdenk9aea9532004-08-01 23:02:45 +0000113 0x0000_0000 0x7fff_ffff DDR 2G
114 0x8000_0000 0x9fff_ffff PCI MEM 512M
115 0xc000_0000 0xdfff_ffff Rapid IO 512M
116 0xe000_0000 0xe00f_ffff CCSR 1M
117 0xe200_0000 0xe2ff_ffff PCI IO 16M
118 0xf000_0000 0xf7ff_ffff SDRAM 128M
119 0xf800_0000 0xf80f_ffff BCSR 1M
120 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
wdenk547b4cb2004-06-09 00:51:50 +0000121
1222.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You
123 can download them from linuxppc-2.4 public source. Please make sure the
124 kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two
125 default configuration files as your starting points to configure the
126 kernel:
Stefan Roesea47a12b2010-04-15 16:07:28 +0200127 arch/powerpc/configs/mpc8540_ads_defconfig
128 arch/powerpc/configs/mpc8560_ads_defconfig
wdenk42d1f032003-10-15 23:53:47 +0000129
1303. DEFINITIONS AND COMPILATION
wdenk48abe7b2004-06-09 10:15:00 +0000131
wdenk0ac6f8b2004-07-09 23:27:13 +00001323.1 Explanation on NEW definitions in:
133 include/configs/MPC8540ADS.h
134 include/configs/MPC8560ADS.h
135
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200136 CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
wdenk9aea9532004-08-01 23:02:45 +0000137 CONFIG_E500 BOOKE e500 family(Motorola)
138 CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
York Sun7f825212016-11-16 11:13:06 -0800139 CONFIG_ARCH_MPC8540 MPC8540 specific
wdenk9aea9532004-08-01 23:02:45 +0000140 CONFIG_MPC8540ADS MPC8540ADS board specific
141 CONFIG_MPC8560ADS MPC8560ADS board specific
142 CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
143 CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can
144 also manual config the DDR after undef this
wdenk0ac6f8b2004-07-09 23:27:13 +0000145 definition.
wdenk9aea9532004-08-01 23:02:45 +0000146 CONFIG_DDR_ECC only for ECC DDR module
Becky Bruce810c4422010-12-17 17:17:58 -0600147 CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed
148 for more stability.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500149 CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000150
151Other than the above definitions, the rest in the config files are
152straightforward.
153
wdenk42d1f032003-10-15 23:53:47 +0000154
wdenk42d1f032003-10-15 23:53:47 +00001553.2 Compilation
wdenk42d1f032003-10-15 23:53:47 +0000156
wdenk0ac6f8b2004-07-09 23:27:13 +0000157 Assuming you're using BASH shell:
158
159 export CROSS_COMPILE=your-cross-compile-prefix
160 cd u-boot
161 make distclean
162 make MPC8560ADS_config (or make MPC8540ADS_config)
163 make
wdenk48abe7b2004-06-09 10:15:00 +0000164
wdenk547b4cb2004-06-09 00:51:50 +00001654. Notes:
wdenk48abe7b2004-06-09 10:15:00 +0000166
wdenk547b4cb2004-06-09 00:51:50 +00001674.1 When connecting with kermit, the following commands must be present.in
wdenk0ac6f8b2004-07-09 23:27:13 +0000168 your .kermrc file. These are especially important when booting as
169 MPC8560, as the serial console will not work without them:
wdenk547b4cb2004-06-09 00:51:50 +0000170
wdenk0ac6f8b2004-07-09 23:27:13 +0000171 set speed 115200
172 set carrier-watch off
173 set handshake none
174 set flow-control none
175 robust
wdenk547b4cb2004-06-09 00:51:50 +0000176
wdenk547b4cb2004-06-09 00:51:50 +0000177
wdenk0ac6f8b2004-07-09 23:27:13 +00001784.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC
179 ethernet. If that happens, you can try the following steps to make
180 network work:
181
182 MPC8560ADS>tftp 1000000 pImage
183 (if it hangs, use Ctrl-C to quit)
184 MPC8560ADS>nm fdf24524
185 >0
186 >1
187 >. (to quit this memory operation)
188 MPC8560ADS>tftp 1000000 pImage
189
1904.3 If you're one of the early developers using the Rev1 8540/8560 chips,
191 please use U-Boot 1.0.0, as the newer silicon will only support Rev2
192 and future revisions of 8540/8560.
193
wdenk547b4cb2004-06-09 00:51:50 +0000194
Bin Menga1875592016-02-05 19:30:11 -08001954.4 Reflash U-Boot Image using U-Boot
wdenk547b4cb2004-06-09 00:51:50 +0000196
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500197 tftp 10000 u-boot.bin
198 protect off fff80000 ffffffff
199 erase fff80000 ffffffff
200 cp.b 10000 fff80000 80000
wdenk547b4cb2004-06-09 00:51:50 +0000201
wdenk42d1f032003-10-15 23:53:47 +0000202
wdenk0ac6f8b2004-07-09 23:27:13 +00002034.5 Reflash U-Boot with a BDI-2000
wdenk48abe7b2004-06-09 10:15:00 +0000204
wdenk9aea9532004-08-01 23:02:45 +0000205 BDI> erase 0xFFF80000 0x4000 0x20
wdenk0ac6f8b2004-07-09 23:27:13 +0000206 BDI> prog 0xfff80000 u-boot.bin.8560ads
207 BDI> verify
208
209
wdenk9aea9532004-08-01 23:02:45 +00002105. Screen dump MPC8540ADS board
wdenk42d1f032003-10-15 23:53:47 +0000211
wdenk9aea9532004-08-01 23:02:45 +0000212U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25)
213
214Freescale PowerPC
215 Core: E500, Version: 2.0, (0x80200020)
216 System: 8540, Version: 2.0, (0x80300020)
217 Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
218 L1 D-cache 32KB, L1 I-cache 32KB enabled.
219Board: ADS
220 PCI1: 32 bit, 66 MHz (compiled)
wdenk42d1f032003-10-15 23:53:47 +0000221I2C: ready
wdenk9aea9532004-08-01 23:02:45 +0000222DRAM: Initializing
223 SDRAM: 64 MB
224 DDR: 256 MB
wdenk42d1f032003-10-15 23:53:47 +0000225FLASH: 16 MB
226L2 cache enabled: 256KB
227*** Warning - bad CRC, using default environment
228
229In: serial
230Out: serial
231Err: serial
wdenk9aea9532004-08-01 23:02:45 +0000232Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
233MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
234MOTO ENET2: PHY is Davicom DM9161E (181b881)
235MOTO ENET0, MOTO ENET1, MOTO ENET2
wdenk42d1f032003-10-15 23:53:47 +0000236Hit any key to stop autoboot: 0
wdenk9aea9532004-08-01 23:02:45 +0000237=>
238=> fli
wdenk42d1f032003-10-15 23:53:47 +0000239
240Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
241 Size: 16 MB in 64 Sectors
242 Sector Start Addresses:
wdenk9aea9532004-08-01 23:02:45 +0000243 FF000000 FF040000 FF080000 FF0C0000 FF100000
244 FF140000 FF180000 FF1C0000 FF200000 FF240000
245 FF280000 FF2C0000 FF300000 FF340000 FF380000
246 FF3C0000 FF400000 FF440000 FF480000 FF4C0000
247 FF500000 FF540000 FF580000 FF5C0000 FF600000
248 FF640000 FF680000 FF6C0000 FF700000 FF740000
249 FF780000 FF7C0000 FF800000 FF840000 FF880000
250 FF8C0000 FF900000 FF940000 FF980000 FF9C0000
251 FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
252 FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
253 FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
254 FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
255 FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
wdenk42d1f032003-10-15 23:53:47 +0000256
wdenk9aea9532004-08-01 23:02:45 +0000257=> bdinfo
wdenk42d1f032003-10-15 23:53:47 +0000258memstart = 0x00000000
wdenk9aea9532004-08-01 23:02:45 +0000259memsize = 0x10000000
wdenk42d1f032003-10-15 23:53:47 +0000260flashstart = 0xFF000000
261flashsize = 0x01000000
262flashoffset = 0x00000000
263sramstart = 0x00000000
264sramsize = 0x00000000
wdenk9aea9532004-08-01 23:02:45 +0000265immr_base = 0xE0000000
266bootflags = 0xE4013F80
267intfreq = 825 MHz
268busfreq = 330 MHz
269ethaddr = 00:E0:0C:00:00:FD
270eth1addr = 00:E0:0C:00:01:FD
271eth2addr = 00:E0:0C:00:02:FD
272IP addr = 192.168.1.253
wdenk42d1f032003-10-15 23:53:47 +0000273baudrate = 115200 bps
wdenk9aea9532004-08-01 23:02:45 +0000274
275
276=> printenv
277bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
278ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
279nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
280bootdelay=10
wdenk42d1f032003-10-15 23:53:47 +0000281baudrate=115200
282loads_echo=1
wdenk9aea9532004-08-01 23:02:45 +0000283ethaddr=00:E0:0C:00:00:FD
284eth1addr=00:E0:0C:00:01:FD
285eth2addr=00:E0:0C:00:02:FD
286ipaddr=192.168.1.253
287serverip=192.168.1.1
288rootpath=/nfsroot
289gatewayip=192.168.1.1
290netmask=255.255.255.0
291hostname=unknown
292bootfile=your.uImage
293loadaddr=200000
294netdev=eth0
295consoledev=ttyS0
296ramdiskaddr=400000
297ramdiskfile=your.ramdisk.u-boot
wdenk42d1f032003-10-15 23:53:47 +0000298stdin=serial
299stdout=serial
300stderr=serial
wdenk9aea9532004-08-01 23:02:45 +0000301ethact=MOTO ENET0
wdenk42d1f032003-10-15 23:53:47 +0000302
wdenk9aea9532004-08-01 23:02:45 +0000303Environment size: 1020/8188 bytes